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Message-ID: <vqzon3svfqvk3poz76jm5x5gf4rd6vkygegonafcprmkejt4aq@5kwlwytg3ulk>
Date: Thu, 25 Sep 2025 06:06:33 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Vikash Garodia <vikash.garodia@....qualcomm.com>
Cc: Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Bryan O'Donoghue <bod@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, linux-arm-msm@...r.kernel.org,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Vishnu Reddy <quic_bvisredd@...cinc.com>
Subject: Re: [PATCH 1/8] media: dt-bindings: qcom-kaanapali-iris: Add
kaanapali video codec binding
On Thu, Sep 25, 2025 at 04:44:39AM +0530, Vikash Garodia wrote:
> Kaanapali SOC brings in the new generation of video IP i.e iris4. When
> compared to previous generation, iris3x, it has,
> - separate power domains for stream and pixel processing hardware blocks
> (bse and vpp).
> - additional power domain for apv codec.
> - power domains for individual pipes (VPPx).
> - different clocks and reset lines.
>
> There are variants of this hardware, where only a single VPP pipe would
> be functional (VPP0), and APV may not be present. In such case, the
> hardware can be enabled without those 2 related power doamins, and
> corresponding clocks. This explains the min entries for power domains
> and clocks.
> Iommus include all the different stream-ids which can be possibly
> generated by vpu4 video hardware in both secure and non secure
> execution mode.
>
> This patch depends on following patches
> https://lore.kernel.org/all/20250924-knp-interconnect-v1-1-4c822a72141c@oss.qualcomm.com/
> https://lore.kernel.org/all/20250924-knp-clk-v1-3-29b02b818782@oss.qualcomm.com/
This doesn't belong to the commit message. But you also can drop this
dependency alltogether. Could you please do it?
>
> Signed-off-by: Vikash Garodia <vikash.garodia@....qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-iris.yaml | 236 +++++++++++++++++++++
> 1 file changed, 236 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f3528d514fe29771227bee5f156962fedb1ea9cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-iris.yaml
> @@ -0,0 +1,236 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-iris.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm kaanapali iris video encode and decode accelerators
> +
> +maintainers:
> + - Vikash Garodia <vikash.garodia@....qualcomm.com>
> + - Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>
> +
> +description:
> + The iris video processing unit is a video encode and decode accelerator
> + present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-iris
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + minItems: 5
> + maxItems: 7
> +
> + power-domain-names:
> + items:
> + - const: venus
> + - const: vcodec0
> + - const: vpp0
> + - const: vpp1
> + - const: apv
> + - const: mxc
> + - const: mmcx
> +
> + clocks:
> + minItems: 8
> + maxItems: 10
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: core
> + - const: vcodec0_core
> + - const: iface1
> + - const: core_freerun
> + - const: vcodec0_core_freerun
> + - const: vcodec_bse
> + - const: vcodec_vpp0
> + - const: vcodec_vpp1
> + - const: vcodec_apv
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: cpu-cfg
> + - const: video-mem
> +
> + resets:
> + maxItems: 4
> +
> + reset-names:
> + items:
> + - const: bus0
> + - const: bus1
> + - const: core_freerun_reset
> + - const: vcodec0_core_freerun_reset
> +
> + iommus:
> + minItems: 3
> + maxItems: 8
> +
> + memory-region:
> + maxItems: 1
> +
> + dma-coherent: true
> +
> + operating-points-v2: true
> +
> + opp-table:
> + type: object
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - power-domain-names
> + - clocks
> + - clock-names
> + - interconnects
> + - interconnect-names
> + - resets
> + - reset-names
> + - iommus
> + - dma-coherent
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + video-codec@...0000 {
> + compatible = "qcom,kaanapali-iris";
> +
> + reg = <0x02000000 0xf0000>;
> +
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + power-domains = <&video_cc_mvs0c_gdsc>,
> + <&video_cc_mvs0_gdsc>,
> + <&video_cc_mvs0_vpp0_gdsc>,
> + <&video_cc_mvs0_vpp1_gdsc>,
> + <&video_cc_mvs0a_gdsc>,
> + <&rpmhpd RPMHPD_MXC>,
> + <&rpmhpd RPMHPD_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "vpp0",
> + "vpp1",
> + "apv",
> + "mxc",
> + "mmcx";
> +
> + operating-points-v2 = <&iris_opp_table>;
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&video_cc_mvs0c_clk>,
> + <&video_cc_mvs0_clk>,
> + <&gcc GCC_VIDEO_AXI1_CLK>,
> + <&video_cc_mvs0c_freerun_clk>,
> + <&video_cc_mvs0_freerun_clk>,
> + <&video_cc_mvs0b_clk>,
> + <&video_cc_mvs0_vpp0_clk>,
> + <&video_cc_mvs0_vpp1_clk>,
> + <&video_cc_mvs0a_clk>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core",
> + "iface1",
> + "core_freerun",
> + "vcodec0_core_freerun",
> + "vcodec_bse",
> + "vcodec_vpp0",
> + "vcodec_vpp1",
> + "vcodec_apv";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "cpu-cfg",
> + "video-mem";
> +
> + memory-region = <&video_mem>;
> +
> + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
> + <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
> + <&video_cc_mvs0c_freerun_clk_ares>,
> + <&video_cc_mvs0_freerun_clk_ares>;
> + reset-names = "bus0",
> + "bus1",
> + "core_freerun_reset",
> + "vcodec0_core_freerun_reset";
> +
> + iommus = <&apps_smmu 0x1940 0x0>,
> + <&apps_smmu 0x1943 0x0>,
> + <&apps_smmu 0x1944 0x0>,
> + <&apps_smmu 0x1a20 0x0>;
> +
> + dma-coherent;
> +
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000 240000000 240000000 360000000>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-338000000 {
> + opp-hz = /bits/ 64 <338000000 338000000 338000000 507000000>;
> + required-opps = <&rpmhpd_opp_low_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-420000000 {
> + opp-hz = /bits/ 64 <420000000 420000000 420000000 630000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_svs>;
> + };
> +
> + opp-444000000 {
> + opp-hz = /bits/ 64 <444000000 444000000 444000000 666000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-533000000 {
> + opp-hz = /bits/ 64 <533000000 533000000 533000000 800000000>;
> + required-opps = <&rpmhpd_opp_nom>,
> + <&rpmhpd_opp_nom>;
> + };
> +
> + opp-630000000 {
> + opp-hz = /bits/ 64 <630000000 630000000 630000000 1104000000>;
> + required-opps = <&rpmhpd_opp_turbo>,
> + <&rpmhpd_opp_turbo>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000 630000000 630000000 1260000000>;
> + required-opps = <&rpmhpd_opp_turbo_l0>,
> + <&rpmhpd_opp_turbo_l0>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000 630000000 850000000 1260000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>,
> + <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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