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Message-Id: <20250924-knp-dts-v1-5-3fdbc4b9e1b1@oss.qualcomm.com>
Date: Wed, 24 Sep 2025 17:17:22 -0700
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, aiqun.yu@....qualcomm.com,
tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
yijie.yang@....qualcomm.com,
Jingyi Wang <jingyi.wang@....qualcomm.com>,
Manish Pandey <manish.pandey@....qualcomm.com>
Subject: [PATCH 05/20] arm64: dts: qcom: kaanapali: Add SDC2 nodes for
Kaanapali soc
From: Manish Pandey <manish.pandey@....qualcomm.com>
Add SD Card host controller for kaanapali soc.
Signed-off-by: Manish Pandey <manish.pandey@....qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 104 ++++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 07dc112065d1..ae1721cfbffc 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -908,6 +908,56 @@ lpass_ag_noc: interconnect@...0000 {
#interconnect-cells = <2>;
};
+ sdhc_2: mmc@...4000 {
+ compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+
+ interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ dma-coherent;
+
+ resets = <&gcc GCC_SDCC2_BCR>;
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <160000 100000>;
+ opp-avg-kBps = <50000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ opp-peak-kBps = <200000 120000>;
+ opp-avg-kBps = <104000 0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
pdc: interrupt-controller@...0000 {
compatible = "qcom,kaanapali-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>,
@@ -974,6 +1024,60 @@ qup_uart7_default: qup-uart7-state {
drive-strength = <2>;
bias-disable;
};
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ card-detect-pins {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
sram@...80000 {
--
2.25.1
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