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Message-ID: <498395c652d3f1268ae5e608b11d6bba3ac170ab.camel@phytec.de>
Date: Thu, 25 Sep 2025 07:32:01 +0000
From: Teresa Remmet <t.remmet@...tec.de>
To: Yannic Moog <y.moog@...tec.de>, "kernel@...gutronix.de"
<kernel@...gutronix.de>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>, "robh@...nel.org"
<robh@...nel.org>, "shawnguo@...nel.org" <shawnguo@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
<conor+dt@...nel.org>
CC: "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "upstream@...ts.phytec.de"
<upstream@...ts.phytec.de>
Subject: Re: [Upstream] [PATCH v2 1/3] arm64: dts: imx8mp pollux: add display
overlays
Hello Yannic,
Am Mittwoch, dem 24.09.2025 um 13:59 +0200 schrieb Yannic Moog:
> imx8mp-phyboard-pollux had a display baked into its board dts file.
> However this approach does not truly discribe the hardware and is not
> suitable when using different displays.
> Move display specific description into an overlay and add the
> successor
> display for the phyboard-pollux as an additional overlay.
>
> Signed-off-by: Yannic Moog <y.moog@...tec.de>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 6 +++
> .../imx8mp-phyboard-pollux-etml1010g3dra.dtso | 44
> ++++++++++++++++++
> .../imx8mp-phyboard-pollux-ph128800t006.dtso | 45
> ++++++++++++++++++
> .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 53 +++++-------
> ----------
> 4 files changed, 107 insertions(+), 41 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> index
> 23535ed47631ca8f9db65bec5c07b6a7a7e36525..805ab9e5942bc9e2b9776e92412
> f56e969b6b39a 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -218,7 +218,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> +imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-
> rdk.dtb \
> + imx8mp-phyboard-pollux-etml1010g3dra.dtbo
> +imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-
> rdk.dtb \
> + imx8mp-phyboard-pollux-ph128800t006.dtbo
> imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-
> rdk.dtb imx8mp-phycore-no-eth.dtbo
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-
> pollux-etml1010g3dra.dtso
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..9c14f7818fec807577f4774c0e4
> 8e9daf5014734
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> etml1010g3dra.dtso
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&backlight_lvds1 {
> + brightness-levels = <0 8 16 32 64 128 255>;
> + default-brightness-level = <8>;
> + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
> + num-interpolated-steps = <2>;
> + pwms = <&pwm3 0 50000 0>;
> + status = "okay";
> +};
> +
> +&lcdif2 {
> + status = "okay";
> +};
> +
> +&lvds_bridge {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk
> IMX8MP_VIDEO_PLL1>;
> + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + /*
> + * The LVDS panel uses 72.4 MHz pixel clock, set
> IMX8MP_VIDEO_PLL1 to
> + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3
> scanout
> + * engine can reach accurate pixel clock of exactly 72.4 MHz.
> + */
> + assigned-clock-rates = <0>, <506800000>;
> + status = "okay";
> +};
> +
> +&panel_lvds1 {
> + compatible = "edt,etml1010g3dra";
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-
> pollux-ph128800t006.dtso
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..0df34c50cce7df58322161f0a2f
> 72eaddf2307a7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> ph128800t006.dtso
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/imx8mp-clock.h>
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&backlight_lvds1 {
> + brightness-levels = <0 8 16 32 64 128 255>;
> + default-brightness-level = <8>;
> + enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
> + num-interpolated-steps = <2>;
> + pwms = <&pwm3 0 66667 0>;
> + status = "okay";
> +};
> +
> +&lcdif2 {
> + status = "okay";
> +};
> +
> +&lvds_bridge {
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk
> IMX8MP_VIDEO_PLL1>;
> + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> + /*
> + * The LVDS panel uses 72.4 MHz pixel clock, set
> IMX8MP_VIDEO_PLL1 to
> + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3
> scanout
> + * engine can reach accurate pixel clock of exactly 66.5 MHz.
> + */
> + assigned-clock-rates = <0>, <465500000>;
> + status = "okay";
> +};
> +
> +
> +&panel_lvds1 {
> + compatible = "powertip,ph128800t006-zhc01";
> + status = "okay";
> +};
> +
> +&pwm3 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-
> rdk.dts
> index
> 436152308642270c320e3ae3b21b9e46b923c043..76a9ae34ba469cbc65648f588c6
> 3c4016119821e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> @@ -1,6 +1,6 @@
> -// SPDX-License-Identifier: GPL-2.0
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
I think this is a good idea to update the License of the Pollux file.
But you should move this out to a separate patch to highlight the
change. Then please do the same for the SoM.
Besides this.
Reviewed-by: Teresa Remmet <t.remmet@...tec.de>
Teresa
> /*
> - * Copyright (C) 2020 PHYTEC Messtechnik GmbH
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> * Author: Teresa Remmet <t.remmet@...tec.de>
> */
>
> @@ -8,7 +8,6 @@
>
> #include <dt-bindings/phy/phy-imx8-pcie.h>
> #include <dt-bindings/leds/leds-pca9532.h>
> -#include <dt-bindings/pwm/pwm.h>
> #include <dt-bindings/thermal/thermal.h>
> #include "imx8mp-phycore-som.dtsi"
>
> @@ -21,16 +20,12 @@ chosen {
> stdout-path = &uart1;
> };
>
> - backlight_lvds: backlight {
> + backlight_lvds1: backlight1 {
> compatible = "pwm-backlight";
> - pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_lvds1>;
> - brightness-levels = <0 4 8 16 32 64 128 255>;
> - default-brightness-level = <11>;
> - enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
> - num-interpolated-steps = <2>;
> + pinctrl-names = "default";
> power-supply = <®_lvds1_reg_en>;
> - pwms = <&pwm3 0 50000 0>;
> + status = "disabled";
> };
>
> fan0: fan {
> @@ -43,10 +38,11 @@ fan0: fan {
> #cooling-cells = <2>;
> };
>
> - panel1_lvds: panel-lvds {
> - compatible = "edt,etml1010g3dra";
> - backlight = <&backlight_lvds>;
> + panel_lvds1: panel-lvds1 {
> + /* compatible panel in overlay */
> + backlight = <&backlight_lvds1>;
> power-supply = <®_vcc_3v3_sw>;
> + status = "disabled";
>
> port {
> panel1_in: endpoint {
> @@ -232,32 +228,8 @@ led-3 {
> };
> };
>
> -&lcdif2 {
> - status = "okay";
> -};
> -
> -&lvds_bridge {
> - status = "okay";
> -
> - ports {
> - port@2 {
> - ldb_lvds_ch1: endpoint {
> - remote-endpoint = <&panel1_in>;
> - };
> - };
> - };
> -};
> -
> -&media_blk_ctrl {
> - /*
> - * The LVDS panel on this device uses 72.4 MHz pixel clock,
> - * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
> - * serializer and LCDIFv3 scanout engine can reach accurate
> - * pixel clock of exactly 72.4 MHz.
> - */
> - assigned-clock-rates = <500000000>, <200000000>,
> - <0>, <0>, <500000000>,
> - <506800000>;
> +&ldb_lvds_ch1 {
> + remote-endpoint = <&panel1_in>;
> };
>
> &snvs_pwrkey {
> @@ -282,9 +254,8 @@ &pcie {
> };
>
> &pwm3 {
> - status = "okay";
> - pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_pwm3>;
> + pinctrl-names = "default";
> };
>
> &rv3028 {
>
--
PHYTEC Messtechnik GmbH | Barcelona-Allee 1 | 55129 Mainz, Germany
Geschäftsführer: Dipl.-Ing. Michael Mitezki, Dipl.-Ing. Bodo Huber,
Dipl.-Ing. (FH) Markus Lickes | Handelsregister Mainz HRB 4656 |
Finanzamt Mainz | St.Nr. 26/665/00608, DE 149059855
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