linux-kernel - Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC

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Message-ID: <53d63dd6-a022-4e80-a317-3218976a7474@oss.qualcomm.com>
Date: Thu, 25 Sep 2025 15:39:43 +0800
From: "Aiqun(Maria) Yu" <aiqun.yu@....qualcomm.com>
To: Krzysztof Kozłowski <k.kozlowski.k@...il.com>,
        Jingyi Wang <jingyi.wang@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
        yijie.yang@....qualcomm.com,
        Ronak Raheja <ronak.raheja@....qualcomm.com>
Subject: Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for
 Kaanapali SoC

On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@....qualcomm.com> wrote:
>>
>> From: Ronak Raheja <ronak.raheja@....qualcomm.com>
>>
>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>> (rev. v8) and M31 eUSB2 PHY.
>>
>> Signed-off-by: Ronak Raheja <ronak.raheja@....qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>  1 file changed, 155 insertions(+)
>>
> 
> 
> Second try, without HTML:
> 
> I really don't understand why you created such huge patchset. Year
> ago, two years ago, we were discussing it already and explained that's
> just inflating the patchset without reason.
> 
> New Soc is one logical change. Maybe two. Not 18!

It was previously squashed into the base soc dtsi patch and mark like:
Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
(added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
Jinlong Mao(added coresight).

While it is over 4000+ lines when we squash it together.
Also as offline reviewed with Bjorn, he suggested us to split out the
USB and other parts.

> 
> Not one patch per node or feature.
> 
> This hides big picture, makes difficult to review everything,
> difficult to test. Your patch count for LWN stats doesn't matter to
> us.

With the current splitting, the different author as each co-developer
can get the meaningful LWN stats.>
> NAK and I'm really disappointed I have to repeat the same review .
Currently, there are 10 SoC DTSI patches sent, structured as follows:

SoC initial
Base MTP board
SoC PCIe0
SoC SDC2
SoC USB
SoC remoteproc
SoC SPMI bus, TSENS, RNG, QCrypto, and Coresight
SoC additional features
SoC audio
SoC CAMSS
SoC video

Which parts would you prefer to squash into pls?

-- 
Thx and BRs,
Aiqun(Maria) Yu