linux-kernel - Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <91e73a29-96e3-4a52-addb-0cb954f46c04@app.fastmail.com>
Date: Thu, 25 Sep 2025 11:35:44 +0200
From: "Arnd Bergmann" <arnd@...db.de>
To: Nuno Sá <noname.nuno@...il.com>,
 "Manikanta Guntupalli" <manikanta.guntupalli@....com>,
 "Jorge Marques" <gastmaier@...il.com>, "Arnd Bergmann" <arnd@...nel.org>
Cc: "Alexandre Belloni" <alexandre.belloni@...tlin.com>,
 "Jorge Marques" <jorge.marques@...log.com>,
 "Wolfram Sang" <wsa+renesas@...g-engineering.com>,
 "Frank Li" <Frank.Li@....com>,
 "linux-i3c@...ts.infradead.org" <linux-i3c@...ts.infradead.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "git (AMD-Xilinx)" <git@....com>, "Michal Simek" <michal.simek@....com>
Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers

On Thu, Sep 25, 2025, at 10:58, Nuno Sá wrote:
> On Thu, 2025-09-25 at 08:47 +0000, Guntupalli, Manikanta wrote:
>> > (AMD-Xilinx) <git@....com>; Simek, Michal <michal.simek@....com>
>> > Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers
>> > On Thu, 2025-09-25 at 07:37 +0000, Guntupalli, Manikanta wrote:
>> > > > i3c@...ts.infradead.org; linux-kernel@...r.kernel.org
>> > > > Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers
>> > > > On Wed, Sep 24, 2025 at 10:18:33PM +0200, Arnd Bergmann wrote:
>> > 
>> > I would argue that's something for callers of these functions to care about.
>> If each I3C driver has to handle FIFO endianness individually, it introduces
>> unnecessary duplication and overhead across drivers. Centralizing this in the
>> FIFO access helpers keeps the logic consistent, avoids repeated boilerplate,
>> and reduces the chance of subtle bugs.
>
> I mean, that's what spi and i2c drivers do already. With enum i3c_fifo_endian
> you're already forcing users to care (or know) about endianism so they might as
> well just pass the data in the proper order already (not sure if it's such a big
> 'burden').

Can you give an example of an spi or i2c driver handles a similar
situation to the new i3c driver? As far as I can tell, swapping
the bytes in a FIFO register is very unusual for a hardware design
and probably a mistake rather than an intentional decision.

On the other hand, I can find drivers that are obviously wrong
on big-endian kernels, such as Tegra's i2c_writesl_vi() function
being unintentionally swapped from i2c_writesl() on big-endian.

For the i3c helper, I think Jorge's current version with my
fix should work for every normal driver, and I would not
want to make it more complicated for an obscure case. The
version for the AMD driver can just be in that driver, or
it could be a separate function name in the common header
if there is a chance we'll need it again.

      Arnd