linux-kernel - Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for Kaanapali SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f7b46afd-eeaf-4647-a721-0bf092ab8e09@oss.qualcomm.com>
Date: Thu, 25 Sep 2025 11:46:52 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: "Aiqun(Maria) Yu" <aiqun.yu@....qualcomm.com>,
        Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
        Jingyi Wang <jingyi.wang@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
        yijie.yang@....qualcomm.com,
        Ronak Raheja <ronak.raheja@....qualcomm.com>
Subject: Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for
 Kaanapali SoC

On 9/25/25 9:49 AM, Aiqun(Maria) Yu wrote:
> On 9/25/2025 11:20 AM, Dmitry Baryshkov wrote:
>> On Wed, Sep 24, 2025 at 05:17:23PM -0700, Jingyi Wang wrote:
>>> From: Ronak Raheja <ronak.raheja@....qualcomm.com>
>>>
>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>> (rev. v8) and M31 eUSB2 PHY.
>>>
>>> Signed-off-by: Ronak Raheja <ronak.raheja@....qualcomm.com>
>>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>>  1 file changed, 155 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> index ae1721cfbffc..08ab267bf9a7 100644
>>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>>> @@ -12,6 +12,7 @@
>>>  #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>  #include <dt-bindings/mailbox/qcom-ipcc.h>
>>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>>>  #include <dt-bindings/power/qcom-rpmpd.h>
>>>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>> @@ -958,6 +959,160 @@ opp-202000000 {
>>>  			};
>>>  		};
>>>  
>>> +		usb_1_hsphy: phy@...3000 {
>>
>> No update for GCC clocks?
>>
> 
> could you help to have more detailed comments here pls?
> For this driver phy-qcom-m31-eusb2, only ref clk is needed per my
> current information.

The QMPPHY acts as a clock provider, which we're expected to plug
it back into GCC (and DISP_CC), see e.g. sm8650.dtsi

Konrad