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Message-Id: <20250925-glymur_gcc_usb_fixes-v2-1-ee4619571efe@oss.qualcomm.com>
Date: Thu, 25 Sep 2025 15:49:00 +0530
From: Taniya Das <taniya.das@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Ajit Pandey <quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Taniya Das <taniya.das@....qualcomm.com>
Subject: [PATCH v2] clk: qcom: gcc-glymur: Update the halt check flags for
pipe clocks
The pipe clocks for PCIE and USB are externally sourced and they should
not be polled by the clock driver. Update the halt_check flags to 'SKIP'
to disable polling for these clocks.
This helps avoid the clock status stuck at 'off' warnings, which are
benign, since all consumers of the PHYs must initialize a given instance
before performing any operations.
Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller")
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
---
Changes in v2:
- Update the commit text to add the SoC name "glymur" [Konrad]
- Update the commit subject to add more details [Konrad]
- Add RB [Konrad]
- Fix a typo [Markus Elfring]
- Link to v1: https://lore.kernel.org/r/20250924-glymur_gcc_usb_fixes-v1-1-a90568723e64@oss.qualcomm.com
---
drivers/clk/qcom/gcc-glymur.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c
index 62059120f9720bbac03852c0368f4de3038a559c..d938e7dc5b66ec539c3264a2e212b3d6878b1fde 100644
--- a/drivers/clk/qcom/gcc-glymur.c
+++ b/drivers/clk/qcom/gcc-glymur.c
@@ -6760,7 +6760,7 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x3f088,
- .halt_check = BRANCH_HALT_DELAY,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x3f088,
.hwcg_bit = 1,
.clkr = {
@@ -6816,7 +6816,7 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0xe2078,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe2078,
.hwcg_bit = 1,
.clkr = {
@@ -6872,7 +6872,7 @@ static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
.halt_reg = 0xe1078,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe1078,
.hwcg_bit = 1,
.clkr = {
@@ -6961,7 +6961,7 @@ static struct clk_branch gcc_usb4_0_master_clk = {
static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x2b0f4,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x2b0f4,
.enable_mask = BIT(0),
@@ -6979,7 +6979,7 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
.halt_reg = 0x2b04c,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(11),
@@ -7033,7 +7033,7 @@ static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
.halt_reg = 0x2b0bc,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2b0bc,
.hwcg_bit = 1,
.clkr = {
@@ -7196,7 +7196,7 @@ static struct clk_branch gcc_usb4_1_master_clk = {
static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
.halt_reg = 0x2d118,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x2d118,
.enable_mask = BIT(0),
@@ -7214,7 +7214,7 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
.halt_reg = 0x2d04c,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(12),
@@ -7268,7 +7268,7 @@ static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
.halt_reg = 0x2d0e0,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2d0e0,
.hwcg_bit = 1,
.clkr = {
@@ -7431,7 +7431,7 @@ static struct clk_branch gcc_usb4_2_master_clk = {
static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
.halt_reg = 0xe00f8,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xe00f8,
.enable_mask = BIT(0),
@@ -7449,7 +7449,7 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
.halt_reg = 0xe004c,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x62010,
.enable_mask = BIT(13),
@@ -7503,7 +7503,7 @@ static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
.halt_reg = 0xe00c0,
- .halt_check = BRANCH_HALT_VOTED,
+ .halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe00c0,
.hwcg_bit = 1,
.clkr = {
---
base-commit: ce7f1a983b074f6cf8609068088ca3182c569ee4
change-id: 20250924-glymur_gcc_usb_fixes-898f2190f907
Best regards,
--
Taniya Das <taniya.das@....qualcomm.com>
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