linux-kernel - Re: [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device

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Message-ID: <333dc302-aee1-41a6-8cc7-f0315f3b2169@oss.qualcomm.com>
Date: Thu, 25 Sep 2025 12:31:03 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
Subject: Re: [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter
 device

On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> 
> Add spmi-pmic-arb device for the SPMI PMIC arbiter found on
> Glymur. It has three subnodes corresponding to the SPMI0,
> SPMI1 & SPMI2 bus controllers.
> 
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi | 62 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 2632ef381687c2392f8fad0294901e33887ac4d3..e6e001485747785fd29c606773cba7793bbd2a5c 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2600,6 +2600,68 @@ sram@...f000 {
>  			reg = <0x0 0x0c30f000 0x0 0x400>;
>  		};
>  
> +		pmic_arbiter: arbiter@...0000 {

Is this label going to be used?

> +			compatible = "qcom,glymur-spmi-pmic-arb";
> +			reg = <0x0 0x0c400000 0x0 0x00003000>,
> +			      <0x0 0x0c900000 0x0 0x00400000>,
> +			      <0x0 0x0c4c0000 0x0 0x00400000>,
> +			      <0x0 0x0c403000 0x0 0x00008000>;

Drop the padding from the size fields, please

Konrad

> +			reg-names = "core",
> +				    "chnls",
> +				    "obsrvr",
> +				    "chnl_map";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			qcom,channel = <0>;
> +			qcom,ee = <0>;
> +
> +			spmi_bus0: spmi@...6000 {
> +				reg = <0x0 0x0c426000 0x0 0x00004000>,
> +				      <0x0 0x0c8c0000 0x0 0x00010000>,
> +				      <0x0 0x0c42a000 0x0 0x00008000>;
> +				reg-names = "cnfg",
> +					    "intr",
> +					    "chnl_owner";
> +				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "periph_irq";
> +				interrupt-controller;
> +				#interrupt-cells = <4>;
> +				#address-cells = <2>;
> +				#size-cells = <0>;
> +			};
> +
> +			spmi_bus1: spmi@...7000 {
> +				reg = <0x0 0x0c437000 0x0 0x00004000>,
> +				      <0x0 0x0c8d0000 0x0 0x00010000>,
> +				      <0x0 0x0c43b000 0x0 0x00008000>;
> +				reg-names = "cnfg",
> +					    "intr",
> +					    "chnl_owner";
> +				interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "periph_irq";
> +				interrupt-controller;
> +				#interrupt-cells = <4>;
> +				#address-cells = <2>;
> +				#size-cells = <0>;
> +			};
> +
> +			spmi_bus2: spmi@...000 {
> +				reg = <0x0 0x0c448000 0x0 0x00004000>,
> +				      <0x0 0x0c8e0000 0x0 0x00010000>,
> +				      <0x0 0x0c44c000 0x0 0x00008000>;
> +				reg-names = "cnfg",
> +					    "intr",
> +					    "chnl_owner";
> +				interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "periph_irq";
> +				interrupt-controller;
> +				#interrupt-cells = <4>;
> +				#address-cells = <2>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>  		tlmm: pinctrl@...0000 {
>  			compatible = "qcom,glymur-tlmm";
>  			reg = <0x0 0x0f100000 0x0 0xf00000>;
>