linux-kernel - Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali

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Message-ID: <1c8ae43d-ceba-499d-abe9-8014dab5087d@oss.qualcomm.com>
Date: Thu, 25 Sep 2025 12:56:08 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Jingyi Wang <jingyi.wang@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, aiqun.yu@....qualcomm.com,
        tingwei.zhang@....qualcomm.com, trilok.soni@....qualcomm.com,
        yijie.yang@....qualcomm.com, Qiang Yu <qiang.yu@....qualcomm.com>
Subject: Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0
 on Kaanapali

On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Qiang Yu <qiang.yu@....qualcomm.com>
> 
> Describe PCIe0 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe0.
> 
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
> ---

[...]

> +
> +			pcieport0: pcie@0 {

"pcie0_port0:"

> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +				phys = <&pcie0_phy>;

how about:

device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;

phys = <&pcie0_phy>;

#address-cells = <3>;
#size-cells = <2>;
ranges;

with that:

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Konrad