linux-kernel - [PATCH] PCI: dwc: Support 16-lane operation

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Message-Id: <20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com>
Date: Fri, 26 Sep 2025 14:22:45 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Jingoo Han <jingoohan1@...il.com>, 
 Manivannan Sadhasivam <mani@...nel.org>, 
 Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof Wilczyński <kwilczynski@...nel.org>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>, 
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org, 
 Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH] PCI: dwc: Support 16-lane operation

From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.

Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 3 +++
 drivers/pci/controller/dwc/pcie-designware.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index fce15582c22a93167c6f03c0e3ae74f3d0e68b1a..1d7c2b27005f757d272fe78c4df48daa6628f0a3 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -774,6 +774,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
 	case 8:
 		plc |= PORT_LINK_MODE_8_LANES;
 		break;
+	case 16:
+		plc |= PORT_LINK_MODE_16_LANES;
+		break;
 	default:
 		dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
 		return;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a333ab0b0bbd8c2fc0ee32a5619696178c6b7aa2..ae11a78cc5b9a4202794cfa515e1ee496a4f47c2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -90,6 +90,7 @@
 #define PORT_LINK_MODE_2_LANES		PORT_LINK_MODE(0x3)
 #define PORT_LINK_MODE_4_LANES		PORT_LINK_MODE(0x7)
 #define PORT_LINK_MODE_8_LANES		PORT_LINK_MODE(0xf)
+#define PORT_LINK_MODE_16_LANES		PORT_LINK_MODE(0x1f)
 
 #define PCIE_PORT_LANE_SKEW		0x714
 #define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)

---
base-commit: 8e2755d7779a95dd61d8997ebce33ff8b1efd3fb
change-id: 20250926-topic-pcie_16ln-8b505b7909f4

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@....qualcomm.com>