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Message-ID: <aNX6V6OSIwly1hu4@yzhao56-desk.sh.intel.com>
Date: Fri, 26 Sep 2025 10:28:39 +0800
From: Yan Zhao <yan.y.zhao@...el.com>
To: Rick Edgecombe <rick.p.edgecombe@...el.com>
CC: <kas@...nel.org>, <bp@...en8.de>, <chao.gao@...el.com>,
<dave.hansen@...ux.intel.com>, <isaku.yamahata@...el.com>,
<kai.huang@...el.com>, <kvm@...r.kernel.org>, <linux-coco@...ts.linux.dev>,
<linux-kernel@...r.kernel.org>, <mingo@...hat.com>, <pbonzini@...hat.com>,
<seanjc@...gle.com>, <tglx@...utronix.de>, <x86@...nel.org>,
<vannapurve@...gle.com>
Subject: Re: [PATCH v3 00/16] TDX: Enable Dynamic PAMT
On Thu, Sep 18, 2025 at 04:22:08PM -0700, Rick Edgecombe wrote:
> Hi,
>
> This is 3rd revision of Dynamic PAMT, which is a new feature that reduces
> memory use of TDX.
>
> On v2 (as well as in PUCK) there was some discussion of the
> refcount/locking design tradeoffs for Dynamic PAMT. In v2, I’ve basically
> gone through and tried to make the details around this more reviewable.
> The basic solution is the same as v2, with the changes more about moving
> code around or splitting implementations/optimizations. I’m hoping with
> this v3 we can close on whether that approach is good enough or not.
>
> I think the patch quality is in ok shape, but still need some review.
> Maintainers, please feel free to let us go through this v3 for lower level
> code issues, but I would appreciate engagement on the overall design.
>
> Another open still is performance testing, besides the bit about excluding
> contention of the global lock.
>
> Lastly, Yan raised some last minute doubts internally about TDX module
> locking contention. I’m not sure there is a problem, but we can come to an
> agreement as part of the review.
Yes, I found a contention issue that prevents us from dropping the global lock.
I've also written a sample test that demonstrates this contention.
CPU 0 CPU 1
(a) TDH.PHYMEM.PAMT.ADD(A1, B1, xx1) (b) TDH.PHYMEM.PAMT.ADD(B2, xx2, xx3)
A1, B2 are not from the same 2MB physical range,
B1, B2 are from the same 2MB physical range.
Physical addresses of xx1, xx2, xx3 are irrelevant.
(a) adds PAMT pages B1, xx1 for A1's 2MB physical range.
(b) adds PAMT pages xx2, xx3 for B2's 2MB physical range.
This could happen when host wants to AUG a 4KB page A1. So, it allocates 4KB
pages B1, xx1, and invokes (a).
Then host wants to AUG a 4KB page B2. Since there're no PAMT pages for B2's 2MB
physical range yet, host invokes (b).
(a) needs to hold shared lock of B1's 2MB PAMT entry.
(b) needs to hold exclusive lock of B2's 2MB PAMT entry.
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