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Message-ID: <fb3720a1-f910-49db-b83b-b23e407b13a0@oss.qualcomm.com>
Date: Fri, 26 Sep 2025 15:04:56 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Trilok Soni <trilok.soni@....qualcomm.com>,
"Aiqun(Maria) Yu" <aiqun.yu@....qualcomm.com>,
Krzysztof Kozłowski <k.kozlowski.k@...il.com>,
Jingyi Wang <jingyi.wang@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
tingwei.zhang@....qualcomm.com, yijie.yang@....qualcomm.com,
Ronak Raheja <ronak.raheja@....qualcomm.com>
Subject: Re: [PATCH 06/20] arm64: dts: qcom: kaanapali: Add USB support for
Kaanapali SoC
On 9/25/25 8:26 PM, Trilok Soni wrote:
> On 9/25/2025 12:39 AM, Aiqun(Maria) Yu wrote:
>> On 9/25/2025 9:50 AM, Krzysztof Kozłowski wrote:
>>> On Thu, 25 Sept 2025 at 09:17, Jingyi Wang <jingyi.wang@....qualcomm.com> wrote:
>>>>
>>>> From: Ronak Raheja <ronak.raheja@....qualcomm.com>
>>>>
>>>> Add the base USB devicetree definitions for Kaanapali platform. The overall
>>>> chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY
>>>> (rev. v8) and M31 eUSB2 PHY.
>>>>
>>>> Signed-off-by: Ronak Raheja <ronak.raheja@....qualcomm.com>
>>>> Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 155 ++++++++++++++++++++++++++++++++
>>>> 1 file changed, 155 insertions(+)
>>>>
>>>
>>>
>>> Second try, without HTML:
>>>
>>> I really don't understand why you created such huge patchset. Year
>>> ago, two years ago, we were discussing it already and explained that's
>>> just inflating the patchset without reason.
>>>
>>> New Soc is one logical change. Maybe two. Not 18!
>>
>> It was previously squashed into the base soc dtsi patch and mark like:
>> Written with help from Jyothi Kumar Seerapu(added bus), Ronak Raheja
>> (added USB), Manish Pandey(added SDHCI), Gaurav Kashyap(added crypto),
>> Manaf Meethalavalappu Pallikunhi(added tsens), Qiang Yu(added PCIE) and
>> Jinlong Mao(added coresight).
>>
>> While it is over 4000+ lines when we squash it together.
>> Also as offline reviewed with Bjorn, he suggested us to split out the
>> USB and other parts.
>>
>>>
>>> Not one patch per node or feature.
>>>
>>> This hides big picture, makes difficult to review everything,
>>> difficult to test. Your patch count for LWN stats doesn't matter to
>>> us.
>
> Maria - the point here is to not design the series / code for stats, but
> per maintainer expectations. Though it is difficult to know one preferred guideline.
I believe Krzysztof's explicit mention of LWN might have misguided
Maria into saying getting good stats there is the goal which of course
wouldn't be a good thing for us to solely strive for..
To the best of my knowledge the actual secondary reason (beyond of course
trying to make the series more manageable which I think turned out mostly
successful and I largely agree with Bjorn's other response to this msg)
is to let authors of larger chunks be credited for their work individually
through commit authorship - which I don't think is "gaming" the stats if
the chunks are reasonably sized and the work is nontrivial (just like any
other post-introduction patches would be treated).
If I wrote let's say 35% of the DT and it would be squashed into a single
"add Kaanapali" patch under someone else's name, I would have had rather
mixed feelings as well..
Konrad
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