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Message-ID: <20250930070356.30695-3-jgross@suse.com>
Date: Tue, 30 Sep 2025 09:03:46 +0200
From: Juergen Gross <jgross@...e.com>
To: linux-kernel@...r.kernel.org,
x86@...nel.org
Cc: xin@...or.com,
Juergen Gross <jgross@...e.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"H. Peter Anvin" <hpa@...or.com>
Subject: [PATCH v2 02/12] x86/sev: Replace call of native_wrmsr() with native_wrmsrq()
In sev_es_wr_ghcb_msr() the 64 bit MSR value is split into 2 32 bit
values in order to call native_wrmsr(), which will combine the values
into a 64 bit value again.
Just use native_wrmsrq() instead.
Signed-off-by: Juergen Gross <jgross@...e.com>
---
V2:
- new patch
---
arch/x86/include/asm/sev-internal.h | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/sev-internal.h b/arch/x86/include/asm/sev-internal.h
index 3dfd306d1c9e..f5d6fb3b5916 100644
--- a/arch/x86/include/asm/sev-internal.h
+++ b/arch/x86/include/asm/sev-internal.h
@@ -89,12 +89,7 @@ static inline u64 sev_es_rd_ghcb_msr(void)
static __always_inline void sev_es_wr_ghcb_msr(u64 val)
{
- u32 low, high;
-
- low = (u32)(val);
- high = (u32)(val >> 32);
-
- native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
+ native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val);
}
void snp_register_ghcb_early(unsigned long paddr);
--
2.51.0
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