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Message-ID: <ec1c7d3deca62adca0ee016a3691a4d8b8f0bdb4.camel@mediatek.com>
Date: Tue, 30 Sep 2025 07:51:11 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: Jay Liu (刘博) <Jay.Liu@...iatek.com>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "AngeloGioacchino Del
 Regno" <angelogioacchino.delregno@...labora.com>,
	Yongqiang Niu (牛永强)
	<yongqiang.niu@...iatek.com>, "airlied@...il.com" <airlied@...il.com>,
	"simona@...ll.ch" <simona@...ll.ch>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
	"hsinyi@...omium.org" <hsinyi@...omium.org>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 1/1] drm/mediatek: fix CCORR mtk_ctm_s31_32_to_s1_n
 function issue

Hi, Yongqiang:

I would like you to review this patch.

Regards,
CK

On Sun, 2025-09-21 at 13:53 +0800, Jay Liu wrote:
> if matrixbit is 11,
> The range of color matrix is from 0 to (BIT(12) - 1).
> Values from 0 to (BIT(11) - 1) represent positive numbers,
> values from BIT(11) to (BIT(12) - 1) represent negative numbers.
> For example, -1 need converted to 8191.
> so convert S31.32 to HW Q2.11 format by drm_color_ctm_s31_32_to_qm_n,
> and set int_bits to 2.
> 
> Fixes: 738ed4156fba ("drm/mediatek: Add matrix_bits private data for ccorr")
> Change-Id: Icb2aae1dee21d9ea34f263a54850fee26d97d455
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Signed-off-by: Jay Liu <jay.liu@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 26 +++--------------------
>  1 file changed, 3 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 10d60d2c2a56..634b31346921 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -80,28 +80,7 @@ void mtk_ccorr_stop(struct device *dev)
>  	writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
>  }
>  
> -/* Converts a DRM S31.32 value to the HW S1.n format. */
> -static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> -{
> -	u16 r;
> -
> -	/* Sign bit. */
> -	r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
> -
> -	if ((in & GENMASK_ULL(62, 33)) > 0) {
> -		/* identity value 0x100000000 -> 0x400(mt8183), */
> -		/* identity value 0x100000000 -> 0x800(mt8192), */
> -		/* if bigger this, set it to max 0x7ff. */
> -		r |= GENMASK(n, 0);
> -	} else {
> -		/* take the n+1 most important bits. */
> -		r |= (in >> (32 - n)) & GENMASK(n, 0);
> -	}
> -
> -	return r;
> -}
> -
> -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
> +bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  {
>  	struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
>  	struct drm_property_blob *blob = state->ctm;
> @@ -109,6 +88,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  	const u64 *input;
>  	uint16_t coeffs[9] = { 0 };
>  	int i;
> +	int int_bits = 2;
>  	struct cmdq_pkt *cmdq_pkt = NULL;
>  	u32 matrix_bits = ccorr->data->matrix_bits;
>  
> @@ -119,7 +99,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
>  	input = ctm->matrix;
>  
>  	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> -		coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
> +		coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i], int_bits, matrix_bits);
>  
>  	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
>  		      &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);

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