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Message-Id: <20250930075644.1665970-2-jun.guo@cixtech.com>
Date: Tue, 30 Sep 2025 15:56:42 +0800
From: Jun Guo <jun.guo@...tech.com>
To: peter.chen@...tech.com,
fugang.duan@...tech.com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
broonie@...nel.org
Cc: linux-spi@...r.kernel.org,
michal.simek@....com,
cix-kernel-upstream@...tech.com,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Jun Guo <jun.guo@...tech.com>
Subject: [PATCH 1/3] dt-bindings: spi: spi-cadence: document optional fifo-width DT property
Add documentation for the optional 'fifo-width' device tree property
for the Cadence SPI controller.
Signed-off-by: Jun Guo <jun.guo@...tech.com>
---
.../devicetree/bindings/spi/spi-cadence.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
index 8de96abe9da1..b2e3f217473b 100644
--- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
@@ -62,6 +62,17 @@ properties:
items:
- const: spi
+ fifo-width:
+ description: |
+ This property specifies the FIFO data width (in bits) of the hardware.
+ It must be configured according to the actual FIFO width set during
+ the IP design. For instance, if the hardware FIFO is 32 bits wide,
+ this property should be set to 32.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 8
+ maximum: 32
+ default: 8
+
required:
- compatible
- reg
--
2.34.1
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