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Message-Id: <20250930-a4_a5_add_clock_driver-v1-4-a9acf7951589@amlogic.com>
Date: Tue, 30 Sep 2025 17:37:17 +0800
From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>, Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc: linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org,
Xianwei Zhao <xianwei.zhao@...ogic.com>, Chuan Liu <chuan.liu@...ogic.com>
Subject: [PATCH 04/19] clk: amlogic: Optimize PLL enable timing
From: Chuan Liu <chuan.liu@...ogic.com>
Amlogic PLL locking procedure shall follow this timing sequence:
1 Assert reset signal: Ensures PLL circuits enter known initial state.
2 Deassert lock-detect signal: Avoid lock signal false triggering.
3 Assert enable signal: Powers up PLL supply.
4 udelay(20): Wait for Bandgap and LDO to power up and stabilize.
5 Enable self-adaptation current module (Optional).
6 Deassert reset signal: Releases PLL to begin normal operation.
7 udelay(20): Wait for PLL loop stabilization.
8 Assert lock-detect signal: lock detection circuit starts to work.
9 Monitor lock status signal: Wait for PLL lock completion.
10 If the PLL fails to lock, it should be disabled, This makes the
logic more complete, and also helps save unnecessary power consumption
when the PLL is malfunctioning.
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
---
drivers/clk/meson/clk-pll.c | 68 ++++++++++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 1ea6579a760f..8bddd44d4738 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -353,6 +353,23 @@ static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
return -EIO;
}
+static void meson_clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+
+ /* Put the pll is in reset */
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 1);
+
+ /* Disable the pll */
+ meson_parm_write(clk->map, &pll->en, 0);
+
+ /* Disable PLL internal self-adaption current module */
+ if (MESON_PARM_APPLICABLE(&pll->current_en))
+ meson_parm_write(clk->map, &pll->current_en, 0);
+}
+
static int meson_clk_pll_enable(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
@@ -366,53 +383,48 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
+ /* Disable the PLL lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
-
- /* Take the pll out reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
- meson_parm_write(clk->map, &pll->rst, 0);
+ /* Wait for Bandgap and LDO to power up and stabilize */
+ udelay(20);
/*
* Compared with the previous SoCs, self-adaption current module
* is newly added for A1, keep the new power-on sequence to enable the
* PLL. The sequence is:
- * 1. enable the pll, delay for 10us
+ * 1. enable the pll, ensure a minimum delay of 10μs
* 2. enable the pll self-adaption current module, delay for 40us
* 3. enable the lock detect module
*/
if (MESON_PARM_APPLICABLE(&pll->current_en)) {
- udelay(10);
meson_parm_write(clk->map, &pll->current_en, 1);
- udelay(40);
- }
-
- if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
- meson_parm_write(clk->map, &pll->l_detect, 1);
- meson_parm_write(clk->map, &pll->l_detect, 0);
+ udelay(20);
}
- if (meson_clk_pll_wait_lock(hw))
- return -EIO;
+ /* Take the pll out reset */
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 0);
- return 0;
-}
+ /* Wait for PLL loop stabilization */
+ udelay(20);
-static void meson_clk_pll_disable(struct clk_hw *hw)
-{
- struct clk_regmap *clk = to_clk_regmap(hw);
- struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+ /* Enable the lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 0);
- /* Put the pll is in reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
- meson_parm_write(clk->map, &pll->rst, 1);
+ if (meson_clk_pll_wait_lock(hw)) {
+ /* disable PLL when PLL lock failed. */
+ meson_clk_pll_disable(hw);
+ pr_warn("%s: PLL lock failed!!!\n", clk_hw_get_name(hw));
- /* Disable the pll */
- meson_parm_write(clk->map, &pll->en, 0);
+ return -EIO;
+ }
- /* Disable PLL internal self-adaption current module */
- if (MESON_PARM_APPLICABLE(&pll->current_en))
- meson_parm_write(clk->map, &pll->current_en, 0);
+ return 0;
}
static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.42.0
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