linux-kernel - [GIT PULL 1/5] soc: new SoC support for 6.18

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Message-Id: <ce4be3de-eae9-4a73-9d85-e47976ef8372@app.fastmail.com>
Date: Thu, 02 Oct 2025 00:24:18 +0200
From: "Arnd Bergmann" <arnd@...db.de>
To: "Linus Torvalds" <torvalds@...ux-foundation.org>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-riscv@...ts.infradead.org, soc@...ts.linux.dev
Subject: [GIT PULL 1/5] soc: new SoC support for 6.18

The following changes since commit b320789d6883cc00ac78ce83bccbfe7ed58afcf0:

  Linux 6.17-rc4 (2025-08-31 15:33:07 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git soc-newsoc-6.18

for you to fetch changes up to fee2f45def0379ed140de4db8f998edb1d78e619:

  riscv: dts: eswin: add HiFive Premier P550 board device tree (2025-09-25 08:29:06 +0200)

----------------------------------------------------------------
soc: new SoC support for 6.18

Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC, as
described in [1]:

 "Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
  P550 CPU cluster and the first development board that uses it, the
  SiFive HiFive Premier P550.

  This patch series adds initial device tree and also adds ESWIN
  architecture support.

  Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier
  P550 board using U-Boot 2024.01 and OpenSBI 1.4."

[1] https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/

----------------------------------------------------------------
Darshan Prajapati (2):
      dt-bindings: riscv: Add SiFive P550 CPU compatible
      dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC

Min Lin (2):
      riscv: dts: add initial support for EIC7700 SoC
      riscv: dts: eswin: add HiFive Premier P550 board device tree

Pinkesh Vaghela (1):
      riscv: Add Kconfig option for ESWIN platforms

Pritesh Patel (1):
      dt-bindings: riscv: Add SiFive HiFive Premier P550 board

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 Documentation/devicetree/bindings/riscv/eswin.yaml |  29 ++
 MAINTAINERS                                        |   9 +
 arch/riscv/Kconfig.socs                            |   6 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/eswin/Makefile                 |   2 +
 .../boot/dts/eswin/eic7700-hifive-premier-p550.dts |  29 ++
 arch/riscv/boot/dts/eswin/eic7700.dtsi             | 345 +++++++++++++++++++++
 9 files changed, 423 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
 create mode 100644 arch/riscv/boot/dts/eswin/Makefile
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi