Message-ID: <990a62ee-c7a7-4cdf-9e0a-efc7908a1f2e@arm.com>
Date: Wed, 1 Oct 2025 15:05:02 +0100
From: Steven Price <steven.price@....com>
To: Marc Zyngier <maz@...nel.org>
Cc: kvm@...r.kernel.org, kvmarm@...ts.linux.dev,
 Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
 James Morse <james.morse@....com>, Oliver Upton <oliver.upton@...ux.dev>,
 Suzuki K Poulose <suzuki.poulose@....com>, Zenghui Yu
 <yuzenghui@...wei.com>, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Joey Gouly <joey.gouly@....com>,
 Alexandru Elisei <alexandru.elisei@....com>,
 Christoffer Dall <christoffer.dall@....com>, Fuad Tabba <tabba@...gle.com>,
 linux-coco@...ts.linux.dev,
 Ganapatrao Kulkarni <gankulkarni@...amperecomputing.com>,
 Gavin Shan <gshan@...hat.com>, Shanker Donthineni <sdonthineni@...dia.com>,
 Alper Gun <alpergun@...gle.com>, "Aneesh Kumar K . V"
 <aneesh.kumar@...nel.org>, Emi Kisanuki <fj0570is@...itsu.com>,
 Vishal Annapurve <vannapurve@...gle.com>
Subject: Re: [PATCH v10 03/43] arm64: RME: Add SMC definitions for calling the
 RMM

On 01/10/2025 12:58, Marc Zyngier wrote:
> On Wed, 01 Oct 2025 12:00:14 +0100,
> Steven Price <steven.price@....com> wrote:
>>
>> Hi Marc,
>>
>> On 01/10/2025 11:05, Marc Zyngier wrote:
>>> On Wed, 20 Aug 2025 15:55:23 +0100,
>>> Steven Price <steven.price@....com> wrote:
>>>>
>>>> The RMM (Realm Management Monitor) provides functionality that can be
>>>> accessed by SMC calls from the host.
>>>>
>>>> The SMC definitions are based on DEN0137[1] version 1.0-rel0
>>>>
>>>> [1] https://developer.arm.com/documentation/den0137/1-0rel0/
>>>>
>>>> Reviewed-by: Gavin Shan <gshan@...hat.com>
>>>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>
>>>> Signed-off-by: Steven Price <steven.price@....com>
>>>> ---
>>>> Changes since v9:
>>>>  * Corrected size of 'ripas_value' in struct rec_exit. The spec states
>>>>    this is an 8-bit type with padding afterwards (rather than a u64).
>>>> Changes since v8:
>>>>  * Added RMI_PERMITTED_GICV3_HCR_BITS to define which bits the RMM
>>>>    permits to be modified.
>>>> Changes since v6:
>>>>  * Renamed REC_ENTER_xxx defines to include 'FLAG' to make it obvious
>>>>    these are flag values.
>>>> Changes since v5:
>>>>  * Sorted the SMC #defines by value.
>>>>  * Renamed SMI_RxI_CALL to SMI_RMI_CALL since the macro is only used for
>>>>    RMI calls.
>>>>  * Renamed REC_GIC_NUM_LRS to REC_MAX_GIC_NUM_LRS since the actual
>>>>    number of available list registers could be lower.
>>>>  * Provided a define for the reserved fields of FeatureRegister0.
>>>>  * Fix inconsistent names for padding fields.
>>>> Changes since v4:
>>>>  * Update to point to final released RMM spec.
>>>>  * Minor rearrangements.
>>>> Changes since v3:
>>>>  * Update to match RMM spec v1.0-rel0-rc1.
>>>> Changes since v2:
>>>>  * Fix specification link.
>>>>  * Rename rec_entry->rec_enter to match spec.
>>>>  * Fix size of pmu_ovf_status to match spec.
>>>> ---
>>>>  arch/arm64/include/asm/rmi_smc.h | 269 +++++++++++++++++++++++++++++++
>>>>  1 file changed, 269 insertions(+)
>>>>  create mode 100644 arch/arm64/include/asm/rmi_smc.h
>>>>
>>>> diff --git a/arch/arm64/include/asm/rmi_smc.h b/arch/arm64/include/asm/rmi_smc.h
>>>> new file mode 100644
>>>> index 000000000000..1000368f1bca
>>>> --- /dev/null
>>>> +++ b/arch/arm64/include/asm/rmi_smc.h
>>>
>>> [...]
>>>
>>>> +#define RMI_PERMITTED_GICV3_HCR_BITS	(ICH_HCR_EL2_UIE |		\
>>>> +					 ICH_HCR_EL2_LRENPIE |		\
>>>> +					 ICH_HCR_EL2_NPIE |		\
>>>> +					 ICH_HCR_EL2_VGrp0EIE |		\
>>>> +					 ICH_HCR_EL2_VGrp0DIE |		\
>>>> +					 ICH_HCR_EL2_VGrp1EIE |		\
>>>> +					 ICH_HCR_EL2_VGrp1DIE |		\
>>>> +					 ICH_HCR_EL2_TDIR)
>>>
>>> Why should KVM care about what bits the RMM wants to use? Also, why
>>> should KVM be forbidden to use the TALL0, TALL1 and TC bits? If
>>> interrupt delivery is the host's business, then the RMM has no
>>> business interfering with the GIC programming.
>>
>> The RMM receives the guest's GIC state in a field within the REC entry
>> structure (enter.gicv3_hcr). The RMM spec states that the above is the
>> list of fields that will be considered and that everything else must be
>> 0[1]. So this is used to filter the configuration to make sure it's
>> valid for the RMM.
>>
>> In terms of TALL0/TALL1/TC bits: these control trapping to EL2, and when
>> in a realm guest the RMM is EL2 - so it's up to the RMM to configure
>> these bits appropriately as it is the RMM which will have to deal with
>> the trap.
> 
> And I claim this is *wrong*. Again, if the host is in charge of
> interrupt injection, then the RMM has absolutely no business is
> deciding what can or cannot be trapped. There is zero information
> exposed by these traps that the host is not already aware of.
> 
>> [1] RWVGFJ in the 1.0 spec from
>> https://developer.arm.com/documentation/den0137/latest
> 
> Well, until someone explains what this is protecting against, I
> consider this as broken.

I'm not sure I understand how you want this to work. Ultimately the
realm guest entry is a bounce from NS-EL2 to EL3 to R-EL2 to R-EL1/0. So
the RMM has to have some control over the trapping behaviour for its own
protection. The current spec means that the RMM does not have to
implement the trap handlers for TALL0/TALL1/TC and can simply force
these bits to 0. Allowing the host to enable traps that the RMM isn't
expecting will obviously end in problems.

If your argument is that because the NS host is emulating the GIC it
needs to be able to do these traps, then that's something that can be
fed back to the spec and hopefully improved. In that case the trap
information would be provided in the rec_entry structure and on trap the
RMM would return prepare information in the rec_exit structure. This
could in theory be handled similar to an emulatable data abort with a
new exit reason.

The other approach would be to push more GIC handling into the RMM such
that these trap bits are not needed (i.e. there's no requirement to exit
to the NS host to handle the trap, and the RMM can program them
independently). I'm afraid I don't understand the GIC well enough to
know how these traps are used and how feasible it is for the RMM to just
"do the right thing" here.

>>>> +	union { /* 0x300 */
>>>> +		struct {
>>>> +			u64 gicv3_hcr;
>>>> +			u64 gicv3_lrs[REC_MAX_GIC_NUM_LRS];
>>>> +			u64 gicv3_misr;
>>>
>>> Why do we care about ICH_MISR_EL2? Surely we get everything in the
>>> registers themselves, right? I think this goes back to my question
>>> above: why is the RMM getting in the way of ICH_*_EL2 accesses?
>>
>> As mentioned above, the state of the guest's GIC isn't passed through
>> the CPU's registers, but instead using the rec_enter/rec_exit
>> structures. So unlike a normal guest entry we don't set all the CPU's
>> register state before entering, but instead hand over a shared data
>> structure and the RMM is responsible for actually programming the
>> registers on the CPU. Since many of the registers are (deliberately)
>> unavailable to the host (e.g. all the GPRs) it makes some sense the RMM
>> also handles the GIC registers save/restore.
> 
> And I claim this is nonsense. There is nothing in these registers that
> the host doesn't need to know about, which is why they are basically
> copied over.

Well it's fairly obvious that the host (generally) doesn't need to know
the general purpose registers. And it's fairly clear that confidential
compute would be pretty pointless if the hypervisor leaked those
registers. So I hope we agree that some architectural registers are
going to have to be handled differently from a normal guest.

The GIC is unusual because it's (partly) emulated by the host. The
configuration is also complex because during guest entry rather than
just dropping down to EL1/0 we're actually performing an SMC to EL3 and
world-switching. So I'm not sure to what extent programming the
architectural registers in the normal world would work.

> It all feels just wrong.

I think fundamentally the confusing thing is there are two hypervisors
pretending to be one. Both KVM and the RMM are providing part of the
role of the hypervisor. It would "feel" neater for the RMM to take on
more responsibility of the hypervisor role but that leads to more
complexity in the RMM (whose simplicity is part of the value of CCA) and
potentially less flexibility because you haven't got the functionality
of KVM.

Thanks,
Steve

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