linux-kernel - Re: [PATCH v2] mfd: da9052-spi: change read-mask to write-mask

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Message-ID: <aN4ujFg_uRufUXn-@zeus>
Date: Thu, 2 Oct 2025 10:49:32 +0300
From: Ian Ray <ian.ray@...ealthcare.com>
To: Marcus Folkesson <marcus.folkesson@...il.com>
Cc: Support Opensource <support.opensource@...semi.com>,
	Lee Jones <lee@...nel.org>, Axel Lin <axel.lin@...ics.com>,
	Adam Thomson <Adam.Thomson.Opensource@...semi.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] mfd: da9052-spi: change read-mask to write-mask

On Thu, Oct 02, 2025 at 09:23:21AM +0200, Marcus Folkesson wrote:
> Hello Ian,
> 
> On Wed, Oct 01, 2025 at 04:03:37PM +0300, Ian Ray wrote:
> > Hello Marcus,
> > 
> > On Wed, Sep 25, 2024 at 12:19:53PM +0200, Marcus Folkesson wrote:
> > > Driver has mixed up the R/W bit.
> > > The LSB bit is set on write rather than read.
> > > Change it to avoid nasty things to happen.
> > > 
> > > Fixes: e9e9d3973594 ("mfd: da9052: Avoid setting read_flag_mask for da9052-i2c driver")
> > > Signed-off-by: Marcus Folkesson <marcus.folkesson@...il.com>
> > 
> > Your patch breaks DA9053 SPI communication (for me, at least) on the
> > 6.1.y branch (I have not tested on master).
> > 
> > The datasheets [1] and [2] both refer to R/Wn in the SPI signalling.
> > 
> > What led to the assertion that "The LSB bit is set on write rather
> > than read."?
> > 
> > In the original code "config.read_flag_mask = 1;", is OR'd into the
> > buffer in regmap_set_work_buf_flag_mask.  This sets the "R" bit as
> > expected.
> 
> Hrm.
> 
> I follow you and agree with what you say.
> Could you please read out R19 INTERFACE register?
> Bit 3, R/W POL, deviates from the default value (1) in my setup, which
> is probably the reason why it doesn't work for me without the patch.

-- >8 -- 
# cat /sys/kernel/debug/regmap/spi2.0/registers |grep "^13:"
13: 88
-- >8 -- 

> 
> Your datasheet revision is later than mine, could you plese verify that
> the default value is still 1 for DA9052 in your revision?

Yes it is still 1 (the complete set of defaults for R19 is 10011000).

> 
> If that is the case, either the datasheet is wrong or my chips must
> somehow been preloaded with some values.

Yes, in my understanding these PMICs are highly configurable via OTP.
(Almost every register can be customized.)

> 
> As nobody else has reported any issue I guess it is safer to revert
> this patch.

Agree -- following the datasheet default is probably the right thing to
do here.

For the future, we could consider an optional device tree property to
describe this read/write bit polarity.

Thanks,
Ian

> 
> > 
> > [1] DA9052 CFR0011-120-00 Rev 5, Revision 2.5, 13-Feb-2017, page 67.
> > [2] DA9053 DA9053-00-IDS2n_131017, page 54.
> > 
> > Blue skies,
> > Ian
> 
> 
> Best regards,
> Marcus Folkesson