linux-kernel - Re: [PATCH 4/8] media: iris: Introduce buffer size calculations for vpu4

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Message-ID: <a8e2906c-9812-0a99-297c-4eceb6c426c9@oss.qualcomm.com>
Date: Thu, 2 Oct 2025 15:36:24 +0530
From: Vikash Garodia <vikash.garodia@....qualcomm.com>
To: Bryan O'Donoghue <bod@...nel.org>,
        Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>
Cc: linux-arm-msm@...r.kernel.org, linux-media@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Vishnu Reddy <quic_bvisredd@...cinc.com>
Subject: Re: [PATCH 4/8] media: iris: Introduce buffer size calculations for
 vpu4


On 9/26/2025 6:30 PM, Bryan O'Donoghue wrote:
> On 25/09/2025 00:14, Vikash Garodia wrote:
>> +{
>> +    u32 dma_opb_wr_tlb_y_size = ((frame_width_coded + 15) >> 4) << 7;
>> +    u32 dma_opb_wr_tlb_uv_size = ((frame_width_coded + 15) >> 4) << 7;
>> +    u32 dma_opb_wr2_tlb_y_size = ALIGN((2 * 6 * 64 * frame_height_coded / 8),
>> DMA_ALIGNMENT) *
>> +                       num_vpp_pipes_enc;
>> +    u32 dma_opb_wr2_tlb_uv_size = ALIGN((2 * 6 * 64 * frame_height_coded /
>> 8), DMA_ALIGNMENT) *
>> +                        num_vpp_pipes_enc;
> 
> I find these calculations pretty nebulous and not very obvious to look at.
> 
> A define of some sort with a comment would definitely help other programmers
> reviewing and supporting this code in the future.
> 
> (+ 15 >> 4) << 7 - I'm sure it makes sense when you are looking at a register
> spec in front of your eyes but if you don't have that detail its pretty hard to
> say the values are correct.
> 
> /*
>  * SET_Y_SIZE(x)
>  *     - Add 15 because
>  *     - Shift 4 to lower nibble because
>  *     - Shift the result up 7 because
>  */
> #define SET_Y_SIZE(x)
> 

Sure, i would trying to gather and explain as much info feasible from my side.
At the same time, these calculation for hardware internal buffers have been
there for vpu2/3x, and is being extended for vpu4 in a similar way.

Regards,
Vikash