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Message-ID: <62669f67-d53e-2b56-af8c-e02cdff480a8@linux.intel.com>
Date: Thu, 2 Oct 2025 20:16:42 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Bjorn Helgaas <helgaas@...nel.org>,
Geert Uytterhoeven <geert@...ux-m68k.org>
cc: Niklas Schnelle <schnelle@...ux.ibm.com>, alex.williamson@...hat.com,
clg@...hat.com, mjrosato@...ux.ibm.com, Farhan Ali <alifm@...ux.ibm.com>,
linux-s390@...r.kernel.org, kvm@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>, linux-pci <linux-pci@...r.kernel.org>
Subject: Re: [PATCH v4 04/10] s390/pci: Add architecture specific resource/bus
address translation
On Thu, 2 Oct 2025, Bjorn Helgaas wrote:
> On Thu, Oct 02, 2025 at 02:58:45PM +0200, Niklas Schnelle wrote:
> > On Wed, 2025-09-24 at 10:16 -0700, Farhan Ali wrote:
> > > On s390 today we overwrite the PCI BAR resource address to either an
> > > artificial cookie address or MIO address. However this address is different
> > > from the bus address of the BARs programmed by firmware. The artificial
> > > cookie address was created to index into an array of function handles
> > > (zpci_iomap_start). The MIO (mapped I/O) addresses are provided by firmware
> > > but maybe different from the bus address. This creates an issue when trying
> > > to convert the BAR resource address to bus address using the generic
> > > pcibios_resource_to_bus().
> > >
> > > Implement an architecture specific pcibios_resource_to_bus() function to
> > > correctly translate PCI BAR resource addresses to bus addresses for s390.
> > > Similarly add architecture specific pcibios_bus_to_resource function to do
> > > the reverse translation.
> > >
> > > Signed-off-by: Farhan Ali <alifm@...ux.ibm.com>
> > > ---
> > > arch/s390/pci/pci.c | 74 +++++++++++++++++++++++++++++++++++++++
> > > drivers/pci/host-bridge.c | 4 +--
> > > 2 files changed, 76 insertions(+), 2 deletions(-)
> > >
> >
> > @Bjorn, interesting new development. This actually fixes a current
> > linux-next breakage for us. In linux-next commit 06b77d5647a4 ("PCI:
> > Mark resources IORESOURCE_UNSET when outside bridge windows") from Ilpo
> > (added) breaks PCI on s390 because the check he added in
> > __pci_read_base() doesn't find the resource because the BAR address
> > does not match our MIO / address cookie addresses. With this patch
> > added however the pcibios_bus_to_resource() in __pci_read_base()
> > converts the region correctly and then Ilpo's check works. I was
> > looking at this code quite intensely today wondering about Benjamin's
> > comment if we do need to check for containment rather than exact match.
> > I concluded that I think it is fine as is and was about to give my R-b
> > before Gerd had tracked down the linux-next issue and I found that this
> > fixes it.
> >
> > So now I wonder if we might want to pick this one already to fix the
> > linux-next regression? Either way I'd like to add my:
> >
> > Reviewed-by: Niklas Schnelle <schnelle@...ux.ibm.com>
>
> Hmmm, thanks for the report. I'm about ready to send the pull
> request, and I hate to include something that is known to break s390
> and would require a fix before v6.18. At the same time, I hate to add
> non-trivial code, including more weak functions, this late in the
> window.
>
> 06b77d5647a4 ("PCI: Mark resources IORESOURCE_UNSET when outside
> bridge windows") fixes some bogus messages, but I'm not sure that it's
> actually a functional change. So maybe the simplest at this point
> would be to defer that commit until we can do it and the s390 change
> together.
Hi,
I didn't notice any issues because of the conflict messages, but then, I
didn't look very deeply into what those pnp things were as it seemed bug
in PCI core we want to fix anyway.
Deferring the commit 06b77d5647a4 would be prudent as there seems to be
another problem in Geert's case discussed in the other thread. Even this
short time in next has already served us well by exposing things that need
fixing so better to wait until we've known things resolved.
--
i.
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