linux-kernel - Re: linux-next: manual merge of the kvm tree with the origin tree

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Message-ID: <aN7GyQU6q8fKsJ7J@google.com>
Date: Thu, 2 Oct 2025 11:39:05 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Mark Brown <broonie@...nel.org>
Cc: Paolo Bonzini <pbonzini@...hat.com>, KVM <kvm@...r.kernel.org>, 
	Babu Moger <babu.moger@....com>, Borislav Petkov <bp@...en8.de>, 
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, 
	Linux Next Mailing List <linux-next@...r.kernel.org>, Xin Li <xin@...or.com>
Subject: Re: linux-next: manual merge of the kvm tree with the origin tree

On Thu, Oct 02, 2025, Mark Brown wrote:
> Hi all,
> 
> Today's linux-next merge of the kvm tree got a conflict in:
> 
>   arch/x86/include/asm/cpufeatures.h
> 
> between commit:
> 
>   e19c06219985f ("x86/cpufeatures: Add support for Assignable Bandwidth Monitoring Counters (ABMC)")
> 
> from the origin tree and commit:
> 
>   3c7cb84145336 ("x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions")
> 
> from the kvm tree.
> 
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
> 
> diff --cc arch/x86/include/asm/cpufeatures.h
> index b2a562217d3ff,f1a9f40622cdc..0000000000000
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@@ -496,7 -497,7 +497,8 @@@
>   #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
>   #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
>   #define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
>  -#define X86_FEATURE_MSR_IMM		(21*32+15) /* MSR immediate form instructions */
>  +#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
> ++#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */

Just in case anyone else is starled by the change in bit number, these are
synthetic (or scattered) flags, i.e. the the bit number is arbitrary and not
tied to hardware.