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Message-ID: <93623324232f4ec4dcda830d497ac2890b19215f.1759312886.git.epetron@amazon.de>
Date: Fri, 3 Oct 2025 09:00:44 +0000
From: Evangelos Petrongonas <epetron@...zon.de>
To: Bjorn Helgaas <bhelgaas@...gle.com>, Alex Williamson
<alex.williamson@...hat.com>, "Rafael J . Wysocki" <rafael@...nel.org>, "Len
Brown" <lenb@...nel.org>
CC: Evangelos Petrongonas <epetron@...zon.de>, Pasha Tatashin
<pasha.tatashin@...een.com>, David Matlack <dmatlack@...gle.com>, "Vipin
Sharma" <vipinsh@...gle.com>, Chris Li <chrisl@...nel.org>, Jason Miu
<jasonmiu@...gle.com>, Pratyush Yadav <pratyush@...nel.org>, "Stanislav
Spassov" <stanspas@...zon.de>, <linux-pci@...r.kernel.org>,
<linux-acpi@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<nh-open-source@...zon.com>
Subject: [RFC PATCH 08/13] pci: Save only spec-defined configuration space
Change PCI configuration space save/restore operations by
saving only the regions defined by the PCI specification avoiding any
potential side effects of undefined behaviour.
The current implementation saves the entire configuration space for
device restore operations, including reserved and undefined regions.
This change modifies the save logic to save only architecturally defined
configuration space regions and skipping the undefined areas.
This benefits the PCSC hitrate, as a 4byte access to a region where only
2 bytes are cacheable and 2 are undefined, therefore uncached, will lead
to a HW access instead.
Signed-off-by: Evangelos Petrongonas <epetron@...zon.de>
---
drivers/pci/pci.c | 61 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 56 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index db940f8fd408..3e99baaaf8cd 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1752,11 +1752,62 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
int pci_save_state(struct pci_dev *dev)
{
int i;
- /* XXX: 100% dword access ok here? */
- for (i = 0; i < 16; i++) {
- pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
- pci_dbg(dev, "save config %#04x: %#010x\n",
- i * 4, dev->saved_config_space[i]);
+
+ if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
+ for (i = 0; i < 13; i++) {
+ pci_read_config_dword(dev, i * 4,
+ &dev->saved_config_space[i]);
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ i * 4, dev->saved_config_space[i]);
+ }
+ pci_read_config_byte(
+ dev, PCI_CAPABILITY_LIST,
+ (u8 *)(&dev->saved_config_space[PCI_CAPABILITY_LIST /
+ 4]) +
+ (PCI_CAPABILITY_LIST % 4));
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ PCI_CAPABILITY_LIST,
+ dev->saved_config_space[PCI_CAPABILITY_LIST]);
+ pci_read_config_dword(
+ dev, PCI_INTERRUPT_LINE,
+ &dev->saved_config_space[PCI_INTERRUPT_LINE / 4]);
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ PCI_INTERRUPT_LINE,
+ dev->saved_config_space[PCI_INTERRUPT_LINE]);
+ } else if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+ for (i = 0; i < 13; i++) {
+ pci_read_config_dword(dev, i * 4,
+ &dev->saved_config_space[i]);
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ i * 4, dev->saved_config_space[i]);
+ }
+ pci_read_config_byte(
+ dev, PCI_CAPABILITY_LIST,
+ (u8 *)(&dev->saved_config_space[PCI_CAPABILITY_LIST /
+ 4]) +
+ (PCI_CAPABILITY_LIST % 4));
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ PCI_CAPABILITY_LIST,
+ dev->saved_config_space[PCI_CAPABILITY_LIST]);
+ for (i = 14; i < 16; i++) {
+ pci_read_config_dword(dev, i * 4,
+ &dev->saved_config_space[i]);
+ pci_dbg(dev,
+ "saving config space at offset %#x (reading %#x)\n",
+ i * 4, dev->saved_config_space[i]);
+ }
+ } else {
+ for (i = 0; i < 16; i++) {
+ pci_read_config_dword(dev, i * 4,
+ &dev->saved_config_space[i]);
+ pci_dbg(dev, "save config %#04x: %#010x\n", i * 4,
+ dev->saved_config_space[i]);
+ }
}
dev->state_saved = true;
--
2.47.3
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