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Message-ID: <zyocr7rwdu44jwmr633yke2naitw3dm2hbcx4k64icee4taz2u@2z4zuhvqzplp>
Date: Mon, 6 Oct 2025 02:06:50 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Chu Guangqing <chuguangqing@...pur.com>
Cc: tzimmermann@...e.de, maarten.lankhorst@...ux.intel.com, mripard@...nel.org,
airlied@...il.com, simona@...ll.ch, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH v8 1/1] [DRIVER] gpu: drm: add support for YHGCH ZX1000
soc chipset
On Mon, Sep 29, 2025 at 06:48:31PM +0800, Chu Guangqing wrote:
> add support for ZX1000 BMC soc chipset
>
> The ZX1000 (Z106) chip is a self-developed server management chip of the
> "Zhixin Series" by Yunhai Guochuang. It can monitor the operating status of
> servers in real time and perform various remote management operations on
> servers, including remote system installation, restart, power-on and power-off.
> It supports instruction sets of mainstream processor architectures such as X86,
> ARM, and LoongArch, with fully open firmware and software interfaces that are
> compatible with the third-party application ecosystem.
>
> Signed-off-by: Chu Guangqing <chuguangqing@...pur.com>
> ---
> MAINTAINERS | 6 +
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/yhgch/Kconfig | 11 +
> drivers/gpu/drm/yhgch/Makefile | 4 +
> drivers/gpu/drm/yhgch/yhgch_drm_de.c | 398 +++++++++++++++++++++++++
> drivers/gpu/drm/yhgch/yhgch_drm_drv.c | 308 +++++++++++++++++++
> drivers/gpu/drm/yhgch/yhgch_drm_drv.h | 51 ++++
> drivers/gpu/drm/yhgch/yhgch_drm_i2c.c | 114 +++++++
> drivers/gpu/drm/yhgch/yhgch_drm_regs.h | 208 +++++++++++++
> drivers/gpu/drm/yhgch/yhgch_drm_vdac.c | 134 +++++++++
> 11 files changed, 1237 insertions(+)
> create mode 100644 drivers/gpu/drm/yhgch/Kconfig
> create mode 100644 drivers/gpu/drm/yhgch/Makefile
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_de.c
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_drv.c
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_drv.h
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_i2c.c
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_regs.h
> create mode 100644 drivers/gpu/drm/yhgch/yhgch_drm_vdac.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 520fb4e379a3..8f861858c6e3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -27781,6 +27781,12 @@ S: Maintained
> F: Documentation/input/devices/yealink.rst
> F: drivers/input/misc/yealink.*
>
> +YHGCH DRM DRIVER
> +M: Chu Guangqing <chuguangqing@...pur.com>
> +S: Maintained
> +F: drivers/gpu/drm/yhgch
> +W: https://www.yhgch.com
> +
> Z8530 DRIVER FOR AX.25
> M: Joerg Reuter <jreuter@...na.de>
> L: linux-hams@...r.kernel.org
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index f7ea8e895c0c..8e0b1d12c81f 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -396,6 +396,8 @@ source "drivers/gpu/drm/sprd/Kconfig"
>
> source "drivers/gpu/drm/imagination/Kconfig"
>
> +source "drivers/gpu/drm/yhgch/Kconfig"
> +
> config DRM_HYPERV
> tristate "DRM Support for Hyper-V synthetic video device"
> depends on DRM && PCI && HYPERV
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 4dafbdc8f86a..f344e0173b29 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -231,6 +231,7 @@ obj-y += solomon/
> obj-$(CONFIG_DRM_SPRD) += sprd/
> obj-$(CONFIG_DRM_LOONGSON) += loongson/
> obj-$(CONFIG_DRM_POWERVR) += imagination/
> +obj-$(CONFIG_DRM_YHGCH) += yhgch/
>
> # Ensure drm headers are self-contained and pass kernel-doc
> hdrtest-files := \
> diff --git a/drivers/gpu/drm/yhgch/Kconfig b/drivers/gpu/drm/yhgch/Kconfig
> new file mode 100644
> index 000000000000..887cb66aa305
> --- /dev/null
> +++ b/drivers/gpu/drm/yhgch/Kconfig
> @@ -0,0 +1,11 @@
> +config DRM_YHGCH
> + tristate "DRM Support for YHGCH BMC"
> + depends on DRM && PCI && MMU
> + select DRM_CLIENT_SELECTION
> + select DRM_KMS_HELPER
> + select DRM_GEM_SHMEM_HELPER
> + help
> + Choose this option if you have a YHGCH ZX1000 chipset.
> + If M is selected the module will be called yhgch-drm.
> + IF Y is selected the module will be built into the kernel.
> + IF N is selected the module will be excluded from the kernel.
> diff --git a/drivers/gpu/drm/yhgch/Makefile b/drivers/gpu/drm/yhgch/Makefile
> new file mode 100644
> index 000000000000..30de2fd27f18
> --- /dev/null
> +++ b/drivers/gpu/drm/yhgch/Makefile
> @@ -0,0 +1,4 @@
> +yhgch-drm-y := yhgch_drm_drv.o yhgch_drm_de.o yhgch_drm_vdac.o yhgch_drm_i2c.o
> +
> +obj-$(CONFIG_DRM_YHGCH) += yhgch-drm.o
> +
> diff --git a/drivers/gpu/drm/yhgch/yhgch_drm_de.c b/drivers/gpu/drm/yhgch/yhgch_drm_de.c
> new file mode 100644
> index 000000000000..1a72b5517618
> --- /dev/null
> +++ b/drivers/gpu/drm/yhgch/yhgch_drm_de.c
> @@ -0,0 +1,398 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include <linux/delay.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_gem_atomic_helper.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_gem_shmem_helper.h>
> +#include <drm/drm_format_helper.h>
> +#include <drm/drm_damage_helper.h>
> +#include <drm/drm_fourcc.h>
> +
> +#include <drm/drm_vblank.h>
> +
> +#include "yhgch_drm_drv.h"
> +#include "yhgch_drm_regs.h"
> +
> +struct yhgch_dislay_pll_config {
> + u64 hdisplay;
> + u64 vdisplay;
> + u32 pll1_config_value;
> + u32 pll2_config_value;
> +};
> +
> +static const struct yhgch_dislay_pll_config yhgch_pll_table[] = {
> + { 640, 480, CRT_PLL1_NS_25MHZ, CRT_PLL2_NS_25MHZ },
> + { 800, 600, CRT_PLL1_NS_40MHZ, CRT_PLL2_NS_40MHZ },
> + { 1024, 768, CRT_PLL1_NS_65MHZ, CRT_PLL2_NS_65MHZ },
> + { 1280, 1024, CRT_PLL1_NS_108MHZ, CRT_PLL2_NS_108MHZ },
> + { 1920, 1080, CRT_PLL1_NS_148MHZ, CRT_PLL2_NS_148MHZ },
> +};
> +
> +static int yhgch_plane_atomic_check(struct drm_plane *plane,
> + struct drm_atomic_state *state)
> +{
> + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
> + plane);
> + struct drm_framebuffer *fb = new_plane_state->fb;
> + struct drm_crtc_state *new_crtc_state = NULL;
> +
> + if (!fb)
> + return 0;
This can't happen, please drop.
> +
> + if (new_plane_state->crtc)
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
> +
> + return drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
> + DRM_PLANE_NO_SCALING,
> + DRM_PLANE_NO_SCALING,
> + false, true);
> +}
> +
> +static void yhgch_handle_damage(void __iomem *addr_base, struct iosys_map *src,
> + struct drm_framebuffer *fb,
> + struct drm_rect *clip)
> +{
> + struct iosys_map dst;
> +
> + iosys_map_set_vaddr_iomem(&dst, addr_base);
> + iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
> + drm_fb_memcpy(&dst, fb->pitches, src, fb, clip);
> +}
> +
> +static void yhgch_plane_atomic_update(struct drm_plane *plane,
> + struct drm_atomic_state *state)
> +{
> + struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
> + struct drm_framebuffer *fb = plane_state->fb;
> + struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
> + struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
> + struct yhgch_drm_private *priv = to_yhgch_drm_private(plane->dev);
> + struct drm_atomic_helper_damage_iter iter;
> + struct drm_rect damage;
> + u32 reg;
> + s64 gpu_addr = 0;
> + u32 line_l;
> +
> + if (!plane_state->crtc || !plane_state->fb)
> + return;
> +
> + if (!plane_state->visible)
> + return;
Neither of these can happen, please drop.
> +
> + drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
> + drm_atomic_for_each_plane_damage(&iter, &damage) {
> + yhgch_handle_damage(priv->vram_base, shadow_plane_state->data, fb, &damage);
> + }
> +
> + fb->pitches[0] = (fb->pitches[0] + 15) & ~15;
> +
> + writel(gpu_addr, priv->mmio + YHGCH_CRT_FB_ADDRESS);
Why are you always writing 0 to YHGCH_CRT_FB_ADDRESS here?
> +
> + reg = fb->width * fb->format->cpp[0];
> +
> + line_l = fb->pitches[0];
> + writel(FIELD_PREP(YHGCH_CRT_FB_WIDTH_WIDTH_MASK, reg) |
> + FIELD_PREP(YHGCH_CRT_FB_WIDTH_OFFS_MASK, line_l),
> + priv->mmio + YHGCH_CRT_FB_WIDTH);
> +
> + /* SET PIXEL FORMAT */
> + reg = readl(priv->mmio + YHGCH_CRT_DISP_CTL);
> + reg &= ~YHGCH_CRT_DISP_CTL_FORMAT_MASK;
> + reg |= FIELD_PREP(YHGCH_CRT_DISP_CTL_FORMAT_MASK,
> + fb->format->cpp[0] * 8 / 16);
> + writel(reg, priv->mmio + YHGCH_CRT_DISP_CTL);
> +}
> +
[...]
> +
> +/*
> + * It can operate in one of three modes: 0, 1 or Sleep.
What do 0 and 1 mean here?
> + */
> +void yhgch_set_power_mode(struct yhgch_drm_private *priv, u32 power_mode)
> +{
> + unsigned int control_value = 0;
> + void __iomem *mmio = priv->mmio;
> + u32 input = 1;
> +
> + if (power_mode > YHGCH_PW_MODE_CTL_MODE_SLEEP)
> + return;
> +
> + if (power_mode == YHGCH_PW_MODE_CTL_MODE_SLEEP)
> + input = 0;
> +
> + control_value = readl(mmio + YHGCH_POWER_MODE_CTRL);
> + control_value &= ~(YHGCH_PW_MODE_CTL_MODE_MASK |
> + YHGCH_PW_MODE_CTL_OSC_INPUT_MASK);
> + control_value |= FIELD_PREP(YHGCH_PW_MODE_CTL_MODE_MASK, power_mode);
> + control_value |= FIELD_PREP(YHGCH_PW_MODE_CTL_OSC_INPUT_MASK, input);
> + writel(control_value, mmio + YHGCH_POWER_MODE_CTRL);
> +}
> +
--
With best wishes
Dmitry
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