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Message-ID: <20251006232125.1833979-3-royluo@google.com>
Date: Mon, 6 Oct 2025 23:21:23 +0000
From: Roy Luo <royluo@...gle.com>
To: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Philipp Zabel <p.zabel@...gutronix.de>, Peter Griffin <peter.griffin@...aro.org>,
"André Draszik" <andre.draszik@...aro.org>, Tudor Ambarus <tudor.ambarus@...aro.org>
Cc: Joy Chakraborty <joychakr@...gle.com>, Naveen Kumar <mnkumar@...gle.com>, Roy Luo <royluo@...gle.com>,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org
Subject: [PATCH v1 2/4] dt-bindings: usb: dwc3: Add Google SoC DWC3 USB
Document the DWC3 USB bindings for Google Tensor SoCs.
Signed-off-by: Roy Luo <royluo@...gle.com>
---
.../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
new file mode 100644
index 000000000000..3e8bcc0c2cef
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2025, Google LLC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google DWC3 USB SoC Controller
+
+maintainers:
+ - Roy Luo <royluo@...gle.com>
+
+description:
+ Describes the Google DWC3 USB block, based on Synopsys DWC3 IP.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - google,lga-dwc3
+ - const: google,snps-dwc3
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ description: |
+ The following memory regions must present:
+ - dwc3_core: Core DWC3 IP registers.
+ - host_cfg_csr: Hibernation control registers.
+ - usbint_csr: Hibernation interrupt registers.
+ items:
+ - const: dwc3_core
+ - const: host_cfg_csr
+ - const: usbint_csr
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ interrupt-names:
+ description: |
+ The following interrupts must present:
+ - dwc_usb3: Core DWC3 interrupt.
+ - hs_pme_irq: High speed remote wakeup interrupt for hibernation.
+ - ss_pme_irq: Super speed remote wakeup interrupt for hibernation.
+ items:
+ - const: dwc_usb3
+ - const: hs_pme_irq
+ - const: ss_pme_irq
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ minItems: 3
+ maxItems: 3
+
+ resets:
+ minItems: 5
+ maxItems: 5
+
+ reset-names:
+ items:
+ - const: usbc_non_sticky
+ - const: usbc_sticky
+ - const: usb_drd_bus
+ - const: u2phy_apb
+ - const: usb_top_csr
+
+ power-domains:
+ minItems: 2
+ maxItems: 2
+
+ power-domain-names:
+ description: |
+ The following power domain must present:
+ - usb_psw_pd: The child power domain of usb_top_pd. Turning it on puts the controller
+ into full power state, turning it off puts the controller into power
+ gated state.
+ - usb_top_pd: The parent power domain of usb_psw_pd. Turning it on puts the controller
+ into power gated state, turning it off completely shuts off the
+ controller.
+ items:
+ - const: usb_psw_pd
+ - const: usb_top_pd
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - resets
+ - reset-names
+ - power-domains
+ - power-domain-names
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@...0000 {
+ compatible = "google,lga-dwc3", "google,snps-dwc3";
+ reg = <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x0c450020 0 0x8>;
+ reg-names = "dwc3_core", "host_cfg_csr", "usbint_csr";
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dwc_usb3", "hs_pme_irq", "ss_pme_irq";
+ clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>,
+ <&hsion_u2phy_apb_clk>;
+ clock-names = "usbc_non_sticky", "usbc_sticky", "u2phy_apb";
+ resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>,
+ <&hsion_resets_usb_drd_bus>, <&hsion_resets_u2phy_apb>,
+ <&hsion_resets_usb_top_csr>;
+ reset-names = "usbc_non_sticky", "usbc_sticky",
+ "usb_drd_bus", "u2phy_apb",
+ "usb_top_csr";
+ power-domains = <&hsio_n_usb_psw_pd>, <&hsio_n_usb_pd>;
+ power-domain-names = "usb_psw_pd", "usb_top_pd";
+ phys = <&usb_phy 0>;
+ phy-names = "usb2-phy";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,incr-burst-type-adjustment = <4>;
+ };
+ };
+...
--
2.51.0.618.g983fd99d29-goog
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