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Message-ID: <20251006095036.16367-1-matthias.schiffer@ew.tq-group.com>
Date: Mon, 6 Oct 2025 11:50:36 +0200
From: Matthias Schiffer <matthias.schiffer@...tq-group.com>
To: Nishanth Menon <nm@...com>,
Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux@...tq-group.com,
Matthias Schiffer <matthias.schiffer@...tq-group.com>
Subject: [PATCH] arm64: dts: ti: k3-am642-tqma64xxl: add boot phase tags
Similar to other AM64x-based boards, add boot phase tags to make the
Device Trees usable for firmware/bootloaders without modification.
Supported boot devices are eMMC/SD card, SPI-NOR and USB (both mass
storage and DFU). The I2C EEPROM is included to allow the firmware to
select the correct RAM configuration for different TQMa64xxL variants.
Signed-off-by: Matthias Schiffer <matthias.schiffer@...tq-group.com>
---
.../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 18 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index 8f64d6272b1ba..81e9e047281fd 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -167,6 +167,7 @@ reg_pwm_fan: regulator-pwm-fan {
};
reg_sd: regulator-sd {
+ bootph-all;
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_reg_pins>;
@@ -245,6 +246,7 @@ icssg1_phy0c: ethernet-phy@c {
&main_gpio0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio0_digital_pins>,
<&main_gpio0_hog_pins>;
@@ -263,6 +265,7 @@ &main_gpio0 {
};
&main_gpio1 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_hog_pins>,
<&main_gpio1_pru_pins>;
@@ -332,6 +335,7 @@ &main_spi0 {
/* UART/USB adapter port 1 */
&main_uart0 {
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins>;
status = "okay";
@@ -492,11 +496,17 @@ &mcu_uart1 {
};
&serdes_ln_ctrl {
+ bootph-all;
idle-states = <AM64_SERDES0_LANE0_USB>;
};
+&serdes_refclk {
+ bootph-all;
+};
+
&serdes0 {
serdes0_usb_link: phy@0 {
+ bootph-all;
reg = <0>;
#phy-cells = <0>;
resets = <&serdes_wiz0 1>;
@@ -506,6 +516,7 @@ serdes0_usb_link: phy@0 {
};
&sdhci1 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins>;
bus-width = <4>;
@@ -524,6 +535,7 @@ adc {
};
&usb0 {
+ bootph-all;
/*
* The CDNS USB driver currently doesn't support overcurrent GPIOs,
* so there is no overcurrent detection. The OC pin is configured
@@ -538,6 +550,7 @@ &usb0 {
};
&usbss0 {
+ bootph-all;
ti,vbus-divider;
};
@@ -621,6 +634,7 @@ AM64X_IOPAD(0x00ac, PIN_INPUT, 7)
};
main_gpio0_hog_pins: main-gpio0-hog-pins {
+ bootph-all;
pinctrl-single,pins = <
/* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */
AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7)
@@ -730,6 +744,7 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0)
};
main_mmc1_pins: main-mmc1-pins {
+ bootph-all;
pinctrl-single,pins = <
/* (J19) MMC1_CMD */
AM64X_IOPAD(0x0294, PIN_INPUT, 0)
@@ -751,6 +766,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0)
};
main_mmc1_reg_pins: main-mmc1-reg-pins {
+ bootph-all;
pinctrl-single,pins = <
/* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */
AM64X_IOPAD(0x020c, PIN_OUTPUT, 7)
@@ -791,6 +807,7 @@ AM64X_IOPAD(0x026c, PIN_INPUT, 7)
};
main_uart0_pins: main-uart0-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
/* (D15) UART0_RXD */
AM64X_IOPAD(0x0230, PIN_INPUT, 0)
@@ -861,6 +878,7 @@ AM64X_IOPAD(0x0088, PIN_OUTPUT, 2)
};
main_usb0_pins: main-usb0-pins {
+ bootph-all;
pinctrl-single,pins = <
/* (E19) USB0_DRVVBUS */
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
index ff3b2e0b8dd45..a78297b9fa57e 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
@@ -14,6 +14,7 @@ aliases {
};
memory@...00000 {
+ bootph-pre-ram;
device_type = "memory";
/* 1G RAM - default variant */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
@@ -54,7 +55,12 @@ reg_1v8: regulator-1v8 {
};
};
+&fss {
+ bootph-all;
+};
+
&main_i2c0 {
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins>;
clock-frequency = <400000>;
@@ -67,6 +73,7 @@ tmp1075: temperature-sensor@4a {
};
eeprom0: eeprom@50 {
+ bootph-pre-ram;
compatible = "st,24c02", "atmel,24c02";
reg = <0x50>;
vcc-supply = <®_1v8>;
@@ -89,11 +96,13 @@ eeprom1: eeprom@54 {
};
&ospi0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins>;
flash@0 {
+ bootph-all;
compatible = "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <8>;
@@ -116,6 +125,7 @@ partitions {
};
&sdhci0 {
+ bootph-all;
status = "okay";
non-removable;
disable-wp;
@@ -126,6 +136,7 @@ &sdhci0 {
&main_pmx0 {
main_i2c0_pins: main-i2c0-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
/* (A18) I2C0_SCL */
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0)
@@ -135,6 +146,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0)
};
ospi0_pins: ospi0-pins {
+ bootph-all;
pinctrl-single,pins = <
/* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0)
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
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