lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <35272fd3-c452-4689-813e-03345ba43ea4@kernel.og>
Date: Sun, 5 Oct 2025 20:47:01 -0500
From: Dinh Nguyen <dinguyen@...nel.og>
To: "Romli, Khairul Anuar" <khairul.anuar.romli@...era.com>,
 Dinh Nguyen <dinguyen@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>,
 "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
 open list <linux-kernel@...r.kernel.org>,
 "Ang, Tien Sung" <tien.sung.ang@...era.com>
Subject: Re: [PATCH 1/1] clk: socfpga: agilex5: add clock driver for Agilex5



On 10/5/25 20:39, Romli, Khairul Anuar wrote:
>> On 10/3/25 04:19, Khairul Anuar Romli wrote:
>>> Add the new Clock manager driver to support new Agilex5 platform. The new
>>> driver got rid of the clk_parent_data structures as there are no
>>> 'clock-names'
>>> property in the DT bindings and use parent_names internally. This is
>>> based on
>>> the previous feedback from the maintainer.
>>>
>>> Signed-off-by: Ang Tien Sung <tiensung.ang@...era.com>
>>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@...era.com>
>>> ---
>>>    drivers/clk/socfpga/clk-agilex5.c    | 563 +++++++++++++++++++++++++++
>>>    drivers/clk/socfpga/clk-gate-s10.c   |  53 +++
>>>    drivers/clk/socfpga/clk-periph-s10.c |  41 ++
>>>    drivers/clk/socfpga/clk-pll-s10.c    |  38 +-
>>>    drivers/clk/socfpga/stratix10-clk.h  |  43 ++
>>>    5 files changed, 737 insertions(+), 1 deletion(-)
>>
>> Do you want to add it a Makefile to build it?
> 
> I will add it to a Makefile in V2.
> 
>>
>>>    create mode 100644 drivers/clk/socfpga/clk-agilex5.c
>>>
>>> diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/
>>> clk-agilex5.c
>>> new file mode 100644
>>> index 000000000000..0013fab81357
>>> --- /dev/null
>>> +++ b/drivers/clk/socfpga/clk-agilex5.c
>>> @@ -0,0 +1,563 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2022-2024, Intel Corporation
>>> + * Copyright (C) 2025, Altera Corporation
>>> + */
>>> +#include <linux/slab.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/of_address.h>
>>
>> Remove of_device.h and of_address and just use of.h.
> 
> Will use of.h as suggested.
>>> +#include <linux/platform_device.h>
>>> +#include  <dt-bindings/clock/intel,agilex5-clkmgr.h>
>>> +#include "stratix10-clk.h"
>>> +#include "clk.h"
>>> +
>>
>> <snip>
> 
> Sorry, what is this snip?
> 

It's just a way to cut a chunk of code in the review process so you 
don't have to scroll through the whole email.

Dinh

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ