linux-kernel - Re: [PATCH] irqchip/gic-v5: Fix GIC CDEOI instruction encoding

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Message-ID: <867bx8ysog.wl-maz@kernel.org>
Date: Mon, 06 Oct 2025 16:07:59 +0100
From: Marc Zyngier <maz@...nel.org>
To: Catalin Marinas <catalin.marinas@....com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	Sascha Bischoff <sascha.bischoff@....com>,
	Will Deacon <will@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH] irqchip/gic-v5: Fix GIC CDEOI instruction encoding

On Mon, 06 Oct 2025 14:30:04 +0100,
Catalin Marinas <catalin.marinas@....com> wrote:
> 
> On Mon, Oct 06, 2025 at 12:07:58PM +0200, Lorenzo Pieralisi wrote:
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index 6455db1b54fd..6cf8c46ddde5 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -113,14 +113,14 @@
> >  /* Register-based PAN access, for save/restore purposes */
> >  #define SYS_PSTATE_PAN			sys_reg(3, 0, 4, 2, 3)
> >  
> > -#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt)			\
> > +#define __SYS_INSN(op0, op1, CRn, CRm, op2, Rt)				\
> >  	__emit_inst(0xd5000000					|	\
> >  		    sys_insn((op0), (op1), (CRn), (CRm), (op2))	|	\
> >  		    ((Rt) & 0x1f))
> >  
> > -#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
> > -#define GSB_SYS_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
> > -#define GSB_ACK_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
> > +#define SB_BARRIER_INSN			__SYS_INSN(0, 3, 3, 0, 7, 31)
> > +#define GSB_SYS_BARRIER_INSN		__SYS_INSN(1, 0, 12, 0, 0, 31)
> > +#define GSB_ACK_BARRIER_INSN		__SYS_INSN(1, 0, 12, 0, 1, 31)
> >  
> >  /* Data cache zero operations */
> >  #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
> > @@ -1075,7 +1075,6 @@
> >  #define GICV5_OP_GIC_CDDIS		sys_insn(1, 0, 12, 1, 0)
> >  #define GICV5_OP_GIC_CDHM		sys_insn(1, 0, 12, 2, 1)
> >  #define GICV5_OP_GIC_CDEN		sys_insn(1, 0, 12, 1, 1)
> > -#define GICV5_OP_GIC_CDEOI		sys_insn(1, 0, 12, 1, 7)
> >  #define GICV5_OP_GIC_CDPEND		sys_insn(1, 0, 12, 1, 4)
> >  #define GICV5_OP_GIC_CDPRI		sys_insn(1, 0, 12, 1, 2)
> >  #define GICV5_OP_GIC_CDRCFG		sys_insn(1, 0, 12, 1, 5)
> > @@ -1129,6 +1128,17 @@
> >  #define gicr_insn(insn)			read_sysreg_s(GICV5_OP_GICR_##insn)
> >  #define gic_insn(v, insn)		write_sysreg_s(v, GICV5_OP_GIC_##insn)
> >  
> > +/*
> > + * GIC CDEOI encoding requires Rt to be 0b11111.
> > + * gic_insn() with an immediate value of 0 cannot be used to encode it
> > + * because some compilers do not follow asm inline constraints in
> > + * write_sysreg_s() to turn an immediate 0 value into an XZR as
> > + * MSR source register.
> > + * Use __SYS_INSN to specify its precise encoding explicitly.
> > + */
> > +#define GICV5_CDEOI_INSN		__SYS_INSN(1, 0, 12, 1, 7, 31)
> > +#define gic_cdeoi()			asm volatile(GICV5_CDEOI_INSN)
> 
> Would something like this work? Completely untested (and build still
> going):
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6604fd6f33f4..7aa962f7bdd6 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -1234,7 +1234,10 @@
>  #define write_sysreg_s(v, r) do {					\
>  	u64 __val = (u64)(v);						\
>  	u32 __maybe_unused __check_r = (u32)(r);			\
> -	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
> +	if (__builtin_constant_p(__val) && __val == 0)			\
> +		asm volatile(__msr_s(r, "xzr"));			\
> +	else								\
> +		asm volatile(__msr_s(r, "%x0") : : "r" (__val));	\
>  } while (0)

Ah, looks much better, and keeps the crap localised. The only thing is
that we lose the 'Z' constraint, and that reduces the incentive for
LLVM to have a better codegen. Maybe add a comment for a good measure?

Anyway, FWIW:

Acked-by: Marc Zyngier <maz@...nel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.