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Message-Id: <20251006-tt-bh-dts-v2-3-ed90dc4b3e22@oss.tenstorrent.com>
Date: Mon, 06 Oct 2025 14:21:43 -0700
From: Drew Fustini <fustini@...nel.org>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Alexandre Ghiti <alex@...ti.fr>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Samuel Holland <samuel.holland@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>, Anup Patel <anup@...infault.org>,
Arnd Bergmann <arnd@...db.de>, Joel Stanley <jms@....tenstorrent.com>,
Joel Stanley <joel@....id.au>, Michael Neuling <mikey@...ling.org>,
Nicholas Piggin <npiggin@...il.com>, Michael Ellerman <mpe@...nel.org>,
Andy Gross <agross@...nel.org>,
Anirudh Srinivasan <asrinivasan@...storrent.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Drew Fustini <dfustini@....tenstorrent.com>
Subject: [PATCH v2 3/8] dt-bindings: riscv: cpus: Add SiFive X280
compatible
From: Drew Fustini <dfustini@....tenstorrent.com>
Document compatible for the SiFive X280 RISC-V core.
Acked-by: Rob Herring (Arm) <robh@...nel.org>
Signed-off-by: Drew Fustini <dfustini@....tenstorrent.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 1a0cf0702a45d2df38c48f50d66b3d2ac3715da5..bbc3886282dc5e8c53e54c0acd91608b443f590f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -69,6 +69,7 @@ properties:
- enum:
- sifive,e51
- sifive,u54-mc
+ - sifive,x280
- const: sifive,rocket0
- const: riscv
- const: riscv # Simulator only
--
2.34.1
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