# 0 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-01-03-tre_3s.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-01-03-tre_3s.dts"
# 10 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-01-03-tre_3s.dts"
/dts-v1/;

# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre_3s.dtsi" 1
# 10 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre_3s.dtsi"
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre.dtsi" 1
# 10 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre.dtsi"
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx.dtsi" 1
# 10 "arch/arm/boot/dts/nxp/imx/javad/javad-imx.dtsi"
# 1 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 1




# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/imx6sx-clock.h" 1
# 6 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 7 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 1
# 13 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h" 1
# 14 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 2
# 8 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 9 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 2
# 1 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx-pinfunc.h" 1
# 10 "arch/arm/boot/dts/nxp/imx/javad/../imx6sx.dtsi" 2

/ {
 #address-cells = <1>;
 #size-cells = <1>;





 chosen {};

 aliases {
  can0 = &flexcan1;
  can1 = &flexcan2;
  ethernet0 = &fec1;
  ethernet1 = &fec2;
  gpio0 = &gpio1;
  gpio1 = &gpio2;
  gpio2 = &gpio3;
  gpio3 = &gpio4;
  gpio4 = &gpio5;
  gpio5 = &gpio6;
  gpio6 = &gpio7;
  i2c0 = &i2c1;
  i2c1 = &i2c2;
  i2c2 = &i2c3;
  i2c3 = &i2c4;
  mmc0 = &usdhc1;
  mmc1 = &usdhc2;
  mmc2 = &usdhc3;
  mmc3 = &usdhc4;
  serial0 = &uart1;
  serial1 = &uart2;
  serial2 = &uart3;
  serial3 = &uart4;
  serial4 = &uart5;
  serial5 = &uart6;
  spi0 = &ecspi1;
  spi1 = &ecspi2;
  spi2 = &ecspi3;
  spi3 = &ecspi4;
  spi4 = &ecspi5;
  usb0 = &usbotg1;
  usb1 = &usbotg2;
  usb2 = &usbh;
  usbphy0 = &usbphy1;
  usbphy1 = &usbphy2;
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   compatible = "arm,cortex-a9";
   device_type = "cpu";
   reg = <0>;
   next-level-cache = <&L2>;
   operating-points = <

    996000 1250000
    792000 1175000
    396000 1075000
    198000 975000
   >;
   fsl,soc-operating-points = <

    996000 1175000
    792000 1175000
    396000 1175000
    198000 1175000
   >;
   clock-latency = <61036>;
   #cooling-cells = <2>;
   clocks = <&clks 129>,
     <&clks 20>,
     <&clks 35>,
     <&clks 36>,
     <&clks 4>;
   clock-names = "arm", "pll2_pfd2_396m", "step",
          "pll1_sw", "pll1_sys";
   arm-supply = <&reg_arm>;
   soc-supply = <&reg_soc>;
   nvmem-cells = <&cpu_speed_grade>;
   nvmem-cell-names = "speed_grade";
  };
 };

 ckil: clock-ckil {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <32768>;
  clock-output-names = "ckil";
 };

 osc: clock-osc {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <24000000>;
  clock-output-names = "osc";
 };

 ipp_di0: clock-ipp-di0 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <0>;
  clock-output-names = "ipp_di0";
 };

 ipp_di1: clock-ipp-di1 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <0>;
  clock-output-names = "ipp_di1";
 };

 anaclk1: clock-anaclk1 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <0>;
  clock-output-names = "anaclk1";
 };

 anaclk2: clock-anaclk2 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <0>;
  clock-output-names = "anaclk2";
 };

 mqs: mqs {
  compatible = "fsl,imx6sx-mqs";
  gpr = <&gpr>;
  status = "disabled";
 };

 pmu {
  compatible = "arm,cortex-a9-pmu";
  interrupt-parent = <&gpc>;
  interrupts = <0 94 4>;
 };

 usbphynop1: usbphynop1 {
  compatible = "usb-nop-xceiv";
  #phy-cells = <0>;
 };

 soc: soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  interrupt-parent = <&gpc>;
  ranges;

  ocram_s: sram@8f8000 {
   compatible = "mmio-sram";
   reg = <0x008f8000 0x4000>;
   ranges = <0 0x008f8000 0x4000>;
   #address-cells = <1>;
   #size-cells = <1>;
   clocks = <&clks 157>;
  };

  ocram: sram@900000 {
   compatible = "mmio-sram";
   reg = <0x00900000 0x20000>;
   ranges = <0 0x00900000 0x20000>;
   #address-cells = <1>;
   #size-cells = <1>;
   clocks = <&clks 126>;
  };

  intc: interrupt-controller@a01000 {
   compatible = "arm,cortex-a9-gic";
   #interrupt-cells = <3>;
   interrupt-controller;
   reg = <0x00a01000 0x1000>,
         <0x00a00100 0x100>;
   interrupt-parent = <&intc>;
  };

  L2: cache-controller@a02000 {
   compatible = "arm,pl310-cache";
   reg = <0x00a02000 0x1000>;
   interrupts = <0 92 4>;
   cache-unified;
   cache-level = <2>;
   arm,tag-latency = <4 2 3>;
   arm,data-latency = <4 2 3>;
  };

  gpu: gpu@1800000 {
   compatible = "vivante,gc";
   reg = <0x01800000 0x4000>;
   interrupts = <0 10 4>;
   clocks = <&clks 156>,
     <&clks 156>,
     <&clks 156>;
   clock-names = "bus", "core", "shader";
   power-domains = <&pd_pu>;
  };

  dma_apbh: dma-controller@1804000 {
   compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
   reg = <0x01804000 0x2000>;
   interrupts = <0 13 4>,
         <0 13 4>,
         <0 13 4>,
         <0 13 4>;
   #dma-cells = <1>;
   dma-channels = <4>;
   clocks = <&clks 132>;
  };

  gpmi: nand-controller@1806000 {
   compatible = "fsl,imx6sx-gpmi-nand";
   #address-cells = <1>;
   #size-cells = <1>;
   reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
   reg-names = "gpmi-nand", "bch";
   interrupts = <0 15 4>;
   interrupt-names = "bch";
   clocks = <&clks 192>,
     <&clks 193>,
     <&clks 191>,
     <&clks 190>,
     <&clks 184>;
   clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
          "gpmi_bch_apb", "per1_bch";
   dmas = <&dma_apbh 0>;
   dma-names = "rx-tx";
   status = "disabled";
  };

  aips1: bus@2000000 {
   compatible = "fsl,aips-bus", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   reg = <0x02000000 0x100000>;
   ranges;

   spba-bus@2000000 {
    compatible = "fsl,spba-bus", "simple-bus";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x02000000 0x40000>;
    ranges;

    spdif: spdif@2004000 {
     compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
     reg = <0x02004000 0x4000>;
     interrupts = <0 52 4>;
     dmas = <&sdma 14 18 0>,
            <&sdma 15 18 0>;
     dma-names = "rx", "tx";
     clocks = <&clks 264>,
       <&clks 3>,
       <&clks 197>,
       <&clks 0>, <&clks 0>, <&clks 0>,
       <&clks 82>,
       <&clks 0>, <&clks 0>,
       <&clks 196>;
     clock-names = "core", "rxtx0",
            "rxtx1", "rxtx2",
            "rxtx3", "rxtx4",
            "rxtx5", "rxtx6",
            "rxtx7", "spba";
     status = "disabled";
    };

    ecspi1: spi@2008000 {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
     reg = <0x02008000 0x4000>;
     interrupts = <0 31 4>;
     clocks = <&clks 145>,
       <&clks 145>;
     clock-names = "ipg", "per";
     status = "disabled";
    };

    ecspi2: spi@200c000 {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
     reg = <0x0200c000 0x4000>;
     interrupts = <0 32 4>;
     clocks = <&clks 146>,
       <&clks 146>;
     clock-names = "ipg", "per";
     status = "disabled";
    };

    ecspi3: spi@2010000 {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
     reg = <0x02010000 0x4000>;
     interrupts = <0 33 4>;
     clocks = <&clks 147>,
       <&clks 147>;
     clock-names = "ipg", "per";
     status = "disabled";
    };

    ecspi4: spi@2014000 {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
     reg = <0x02014000 0x4000>;
     interrupts = <0 34 4>;
     clocks = <&clks 148>,
       <&clks 148>;
     clock-names = "ipg", "per";
     status = "disabled";
    };

    uart1: serial@2020000 {
     compatible = "fsl,imx6sx-uart",
           "fsl,imx6q-uart", "fsl,imx21-uart";
     reg = <0x02020000 0x4000>;
     interrupts = <0 26 4>;
     clocks = <&clks 204>,
       <&clks 205>;
     clock-names = "ipg", "per";
     dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
     dma-names = "rx", "tx";
     status = "disabled";
    };

    esai: esai@2024000 {
     compatible = "fsl,imx35-esai";
     reg = <0x02024000 0x4000>;
     interrupts = <0 51 4>;
     clocks = <&clks 239>,
       <&clks 152>,
       <&clks 239>,
       <&clks 196>;
     clock-names = "core", "extal",
            "fsys", "spba";
     dmas = <&sdma 23 21 0>,
            <&sdma 24 21 0>;
     dma-names = "rx", "tx";
     status = "disabled";
    };

    ssi1: ssi@2028000 {
     #sound-dai-cells = <0>;
     compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
     reg = <0x02028000 0x4000>;
     interrupts = <0 46 4>;
     clocks = <&clks 198>,
       <&clks 201>;
     clock-names = "ipg", "baud";
     dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
     dma-names = "rx", "tx";
     fsl,fifo-depth = <15>;
     status = "disabled";
    };

    ssi2: ssi@202c000 {
     #sound-dai-cells = <0>;
     compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
     reg = <0x0202c000 0x4000>;
     interrupts = <0 47 4>;
     clocks = <&clks 199>,
       <&clks 202>;
     clock-names = "ipg", "baud";
     dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
     dma-names = "rx", "tx";
     fsl,fifo-depth = <15>;
     status = "disabled";
    };

    ssi3: ssi@2030000 {
     #sound-dai-cells = <0>;
     compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
     reg = <0x02030000 0x4000>;
     interrupts = <0 48 4>;
     clocks = <&clks 200>,
       <&clks 203>;
     clock-names = "ipg", "baud";
     dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
     dma-names = "rx", "tx";
     fsl,fifo-depth = <15>;
     status = "disabled";
    };

    asrc: asrc@2034000 {
     compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
     reg = <0x02034000 0x4000>;
     interrupts = <0 50 4>;
     clocks = <&clks 235>,
      <&clks 236>, <&clks 0>,
      <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
      <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
      <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
      <&clks 197>, <&clks 0>, <&clks 0>,
      <&clks 196>;
     clock-names = "mem", "ipg", "asrck_0",
      "asrck_1", "asrck_2", "asrck_3", "asrck_4",
      "asrck_5", "asrck_6", "asrck_7", "asrck_8",
      "asrck_9", "asrck_a", "asrck_b", "asrck_c",
      "asrck_d", "asrck_e", "asrck_f", "spba";
     dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
            <&sdma 19 23 1>, <&sdma 20 23 1>,
            <&sdma 21 23 1>, <&sdma 22 23 1>;
     dma-names = "rxa", "rxb", "rxc",
          "txa", "txb", "txc";
     fsl,asrc-rate = <48000>;
     fsl,asrc-width = <16>;
     status = "okay";
    };
   };

   pwm1: pwm@2080000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x02080000 0x4000>;
    interrupts = <0 83 4>;
    clocks = <&clks 186>,
      <&clks 186>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm2: pwm@2084000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x02084000 0x4000>;
    interrupts = <0 84 4>;
    clocks = <&clks 187>,
      <&clks 187>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm3: pwm@2088000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x02088000 0x4000>;
    interrupts = <0 85 4>;
    clocks = <&clks 188>,
      <&clks 188>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm4: pwm@208c000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x0208c000 0x4000>;
    interrupts = <0 86 4>;
    clocks = <&clks 189>,
      <&clks 189>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   flexcan1: can@2090000 {
    compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
    reg = <0x02090000 0x4000>;
    interrupts = <0 110 4>;
    clocks = <&clks 137>,
      <&clks 138>;
    clock-names = "ipg", "per";
    fsl,stop-mode = <&gpr 0x10 1>;
    status = "disabled";
   };

   flexcan2: can@2094000 {
    compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
    reg = <0x02094000 0x4000>;
    interrupts = <0 111 4>;
    clocks = <&clks 139>,
      <&clks 140>;
    clock-names = "ipg", "per";
    fsl,stop-mode = <&gpr 0x10 2>;
    status = "disabled";
   };

   gpt: timer@2098000 {
    compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
    reg = <0x02098000 0x4000>;
    interrupts = <0 55 4>;
    clocks = <&clks 154>,
      <&clks 227>;
    clock-names = "ipg", "per";
   };

   gpio1: gpio@209c000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x0209c000 0x4000>;
    interrupts = <0 66 4>,
          <0 67 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 5 26>;
   };

   gpio2: gpio@20a0000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020a0000 0x4000>;
    interrupts = <0 68 4>,
          <0 69 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 31 20>;
   };

   gpio3: gpio@20a4000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020a4000 0x4000>;
    interrupts = <0 70 4>,
          <0 71 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 51 29>;
   };

   gpio4: gpio@20a8000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020a8000 0x4000>;
    interrupts = <0 72 4>,
          <0 73 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 80 32>;
   };

   gpio5: gpio@20ac000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020ac000 0x4000>;
    interrupts = <0 74 4>,
          <0 75 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 112 24>;
   };

   gpio6: gpio@20b0000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020b0000 0x4000>;
    interrupts = <0 76 4>,
          <0 77 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
   };

   gpio7: gpio@20b4000 {
    compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
    reg = <0x020b4000 0x4000>;
    interrupts = <0 78 4>,
          <0 79 4>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-controller;
    #interrupt-cells = <2>;
    gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
   };

   kpp: keypad@20b8000 {
    compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
    reg = <0x020b8000 0x4000>;
    interrupts = <0 82 4>;
    clocks = <&clks 82>;
    status = "disabled";
   };

   wdog1: watchdog@20bc000 {
    compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
    reg = <0x020bc000 0x4000>;
    interrupts = <0 80 4>;
    clocks = <&clks 82>;
   };

   wdog2: watchdog@20c0000 {
    compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
    reg = <0x020c0000 0x4000>;
    interrupts = <0 81 4>;
    clocks = <&clks 82>;
    status = "disabled";
   };

   clks: clock-controller@20c4000 {
    compatible = "fsl,imx6sx-ccm";
    reg = <0x020c4000 0x4000>;
    interrupts = <0 87 4>,
          <0 88 4>;
    #clock-cells = <1>;
    clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
    clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
   };

   anatop: anatop@20c8000 {
    compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
          "syscon", "simple-mfd";
    reg = <0x020c8000 0x1000>;
    interrupts = <0 49 4>,
          <0 54 4>,
          <0 127 4>;

    reg_vdd1p1: regulator-1p1 {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vdd1p1";
     regulator-min-microvolt = <1000000>;
     regulator-max-microvolt = <1200000>;
     regulator-always-on;
     anatop-reg-offset = <0x110>;
     anatop-vol-bit-shift = <8>;
     anatop-vol-bit-width = <5>;
     anatop-min-bit-val = <4>;
     anatop-min-voltage = <800000>;
     anatop-max-voltage = <1375000>;
     anatop-enable-bit = <0>;
    };

    reg_vdd3p0: regulator-3p0 {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vdd3p0";
     regulator-min-microvolt = <2625000>;
     regulator-max-microvolt = <3400000>;
     regulator-always-on;
     anatop-reg-offset = <0x120>;
     anatop-vol-bit-shift = <8>;
     anatop-vol-bit-width = <5>;
     anatop-min-bit-val = <0>;
     anatop-min-voltage = <2625000>;
     anatop-max-voltage = <3400000>;
     anatop-enable-bit = <0>;
    };

    reg_vdd2p5: regulator-2p5 {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vdd2p5";
     regulator-min-microvolt = <2250000>;
     regulator-max-microvolt = <2750000>;
     regulator-always-on;
     anatop-reg-offset = <0x130>;
     anatop-vol-bit-shift = <8>;
     anatop-vol-bit-width = <5>;
     anatop-min-bit-val = <0>;
     anatop-min-voltage = <2100000>;
     anatop-max-voltage = <2875000>;
     anatop-enable-bit = <0>;
    };

    reg_arm: regulator-vddcore {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vddarm";
     regulator-min-microvolt = <725000>;
     regulator-max-microvolt = <1450000>;
     regulator-always-on;
     anatop-reg-offset = <0x140>;
     anatop-vol-bit-shift = <0>;
     anatop-vol-bit-width = <5>;
     anatop-delay-reg-offset = <0x170>;
     anatop-delay-bit-shift = <24>;
     anatop-delay-bit-width = <2>;
     anatop-min-bit-val = <1>;
     anatop-min-voltage = <725000>;
     anatop-max-voltage = <1450000>;
    };

    reg_pcie: regulator-vddpcie {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vddpcie";
     regulator-min-microvolt = <725000>;
     regulator-max-microvolt = <1450000>;
     anatop-reg-offset = <0x140>;
     anatop-vol-bit-shift = <9>;
     anatop-vol-bit-width = <5>;
     anatop-delay-reg-offset = <0x170>;
     anatop-delay-bit-shift = <26>;
     anatop-delay-bit-width = <2>;
     anatop-min-bit-val = <1>;
     anatop-min-voltage = <725000>;
     anatop-max-voltage = <1450000>;
    };

    reg_soc: regulator-vddsoc {
     compatible = "fsl,anatop-regulator";
     regulator-name = "vddsoc";
     regulator-min-microvolt = <725000>;
     regulator-max-microvolt = <1450000>;
     regulator-always-on;
     anatop-reg-offset = <0x140>;
     anatop-vol-bit-shift = <18>;
     anatop-vol-bit-width = <5>;
     anatop-delay-reg-offset = <0x170>;
     anatop-delay-bit-shift = <28>;
     anatop-delay-bit-width = <2>;
     anatop-min-bit-val = <1>;
     anatop-min-voltage = <725000>;
     anatop-max-voltage = <1450000>;
    };

    tempmon: tempmon {
     compatible = "fsl,imx6sx-tempmon";
     interrupt-parent = <&gpc>;
     interrupts = <0 49 4>;
     fsl,tempmon = <&anatop>;
     nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
     nvmem-cell-names = "calib", "temp_grade";
     clocks = <&clks 6>;
     #thermal-sensor-cells = <0>;
    };
   };

   usbphy1: usbphy@20c9000 {
    compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
    reg = <0x020c9000 0x1000>;
    interrupts = <0 44 4>;
    clocks = <&clks 11>;
    phy-3p0-supply = <&reg_vdd3p0>;
    fsl,anatop = <&anatop>;
   };

   usbphy2: usbphy@20ca000 {
    compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
    reg = <0x020ca000 0x1000>;
    interrupts = <0 45 4>;
    clocks = <&clks 12>;
    phy-3p0-supply = <&reg_vdd3p0>;
    fsl,anatop = <&anatop>;
   };

   snvs: snvs@20cc000 {
    compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
    reg = <0x020cc000 0x4000>;

    snvs_rtc: snvs-rtc-lp {
     compatible = "fsl,sec-v4.0-mon-rtc-lp";
     regmap = <&snvs>;
     offset = <0x34>;
     interrupts = <0 19 4>, <0 20 4>;
    };

    snvs_poweroff: snvs-poweroff {
     compatible = "syscon-poweroff";
     regmap = <&snvs>;
     offset = <0x38>;
     value = <0x60>;
     mask = <0x60>;
     status = "disabled";
    };

    snvs_pwrkey: snvs-powerkey {
     compatible = "fsl,sec-v4.0-pwrkey";
     regmap = <&snvs>;
     interrupts = <0 4 4>;
     linux,keycode = <116>;
     wakeup-source;
     status = "disabled";
    };
   };

   epit1: epit@20d0000 {
    reg = <0x020d0000 0x4000>;
    interrupts = <0 56 4>;
   };

   epit2: epit@20d4000 {
    reg = <0x020d4000 0x4000>;
    interrupts = <0 57 4>;
   };

   src: reset-controller@20d8000 {
    compatible = "fsl,imx6sx-src", "fsl,imx51-src";
    reg = <0x020d8000 0x4000>;
    interrupts = <0 91 4>,
          <0 96 4>;
    #reset-cells = <1>;
   };

   gpc: gpc@20dc000 {
    compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
    reg = <0x020dc000 0x4000>;
    interrupt-controller;
    #interrupt-cells = <3>;
    interrupts = <0 89 4>;
    interrupt-parent = <&intc>;
    clocks = <&clks 82>;
    clock-names = "ipg";

    pgc {
     #address-cells = <1>;
     #size-cells = <0>;

     power-domain@0 {
      reg = <0>;
      #power-domain-cells = <0>;
     };

     pd_pu: power-domain@1 {
      reg = <1>;
      #power-domain-cells = <0>;
      power-supply = <&reg_soc>;
      clocks = <&clks 156>;
     };

     pd_disp: power-domain@2 {
      reg = <2>;
      #power-domain-cells = <0>;
      clocks = <&clks 170>,
        <&clks 173>,
        <&clks 175>,
        <&clks 169>,
        <&clks 174>,
        <&clks 159>,
        <&clks 215>;
     };

     pd_pci: power-domain@3 {
      reg = <3>;
      #power-domain-cells = <0>;
      power-supply = <&reg_pcie>;
     };
    };
   };

   iomuxc: pinctrl@20e0000 {
    compatible = "fsl,imx6sx-iomuxc";
    reg = <0x020e0000 0x4000>;
   };

   gpr: syscon@20e4000 {
    compatible = "fsl,imx6sx-iomuxc-gpr",
          "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x020e4000 0x4000>;

    lvds_bridge: bridge@18 {
     compatible = "fsl,imx6sx-ldb";
     reg = <0x18 0x4>;
     clocks = <&clks 176>;
     clock-names = "ldb";
     status = "disabled";

     ports {
      #address-cells = <1>;
      #size-cells = <0>;

      port@0 {
       reg = <0>;

       ldb_from_lcdif1: endpoint {
       };
      };

      port@1 {
       reg = <1>;

       ldb_lvds_ch0: endpoint {
       };
      };
     };
    };
   };

   sdma: dma-controller@20ec000 {
    compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
    reg = <0x020ec000 0x4000>;
    interrupts = <0 2 4>;
    clocks = <&clks 82>,
      <&clks 195>;
    clock-names = "ipg", "ahb";
    #dma-cells = <3>;

    fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
   };
  };

  aips2: bus@2100000 {
   compatible = "fsl,aips-bus", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   reg = <0x02100000 0x100000>;
   ranges;

   crypto: crypto@2100000 {
    compatible = "fsl,sec-v4.0";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x2100000 0x10000>;
    ranges = <0 0x2100000 0x10000>;
    interrupt-parent = <&intc>;
    clocks = <&clks 134>,
      <&clks 135>,
      <&clks 136>,
      <&clks 213>;
    clock-names = "mem", "aclk", "ipg", "emi_slow";

    sec_jr0: jr@1000 {
     compatible = "fsl,sec-v4.0-job-ring";
     reg = <0x1000 0x1000>;
     interrupts = <0 105 4>;
    };

    sec_jr1: jr@2000 {
     compatible = "fsl,sec-v4.0-job-ring";
     reg = <0x2000 0x1000>;
     interrupts = <0 106 4>;
    };
   };

   usbotg1: usb@2184000 {
    compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
    reg = <0x02184000 0x200>;
    interrupts = <0 43 4>;
    clocks = <&clks 208>;
    fsl,usbphy = <&usbphy1>;
    fsl,usbmisc = <&usbmisc 0>;
    ahb-burst-config = <0x0>;
    tx-burst-size-dword = <0x10>;
    rx-burst-size-dword = <0x10>;
    status = "disabled";
   };

   usbotg2: usb@2184200 {
    compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
    reg = <0x02184200 0x200>;
    interrupts = <0 42 4>;
    clocks = <&clks 208>;
    fsl,usbphy = <&usbphy2>;
    fsl,usbmisc = <&usbmisc 1>;
    ahb-burst-config = <0x0>;
    tx-burst-size-dword = <0x10>;
    rx-burst-size-dword = <0x10>;
    status = "disabled";
   };

   usbh: usb@2184400 {
    compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
    reg = <0x02184400 0x200>;
    interrupts = <0 40 4>;
    clocks = <&clks 208>;
    fsl,usbphy = <&usbphynop1>;
    fsl,usbmisc = <&usbmisc 2>;
    phy_type = "hsic";
    dr_mode = "host";
    ahb-burst-config = <0x0>;
    tx-burst-size-dword = <0x10>;
    rx-burst-size-dword = <0x10>;
    status = "disabled";
   };

   usbmisc: usbmisc@2184800 {
    #index-cells = <1>;
    compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
    reg = <0x02184800 0x200>;
    clocks = <&clks 208>;
   };

   fec1: ethernet@2188000 {
    compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
    reg = <0x02188000 0x4000>;
    interrupt-names = "int0", "pps";
    interrupts = <0 118 4>,
          <0 119 4>;
    clocks = <&clks 172>,
      <&clks 225>,
      <&clks 228>,
      <&clks 17>,
      <&clks 228>;
    clock-names = "ipg", "ahb", "ptp",
           "enet_clk_ref", "enet_out";
    fsl,num-tx-queues = <3>;
    fsl,num-rx-queues = <3>;
    fsl,stop-mode = <&gpr 0x10 3>;
    status = "disabled";
   };

   mlb: mlb@218c000 {
    reg = <0x0218c000 0x4000>;
    interrupts = <0 53 4>,
          <0 117 4>,
          <0 126 4>;
    clocks = <&clks 178>;
    status = "disabled";
   };

   usdhc1: mmc@2190000 {
    compatible = "fsl,imx6sx-usdhc";
    reg = <0x02190000 0x4000>;
    interrupts = <0 22 4>;
    clocks = <&clks 209>,
      <&clks 209>,
      <&clks 209>;
    clock-names = "ipg", "ahb", "per";
    bus-width = <4>;
    fsl,tuning-start-tap = <20>;
    fsl,tuning-step = <2>;
    status = "disabled";
   };

   usdhc2: mmc@2194000 {
    compatible = "fsl,imx6sx-usdhc";
    reg = <0x02194000 0x4000>;
    interrupts = <0 23 4>;
    clocks = <&clks 210>,
      <&clks 210>,
      <&clks 210>;
    clock-names = "ipg", "ahb", "per";
    bus-width = <4>;
    fsl,tuning-start-tap = <20>;
    fsl,tuning-step = <2>;
    status = "disabled";
   };

   usdhc3: mmc@2198000 {
    compatible = "fsl,imx6sx-usdhc";
    reg = <0x02198000 0x4000>;
    interrupts = <0 24 4>;
    clocks = <&clks 211>,
      <&clks 211>,
      <&clks 211>;
    clock-names = "ipg", "ahb", "per";
    bus-width = <4>;
    fsl,tuning-start-tap = <20>;
    fsl,tuning-step = <2>;
    status = "disabled";
   };

   usdhc4: mmc@219c000 {
    compatible = "fsl,imx6sx-usdhc";
    reg = <0x0219c000 0x4000>;
    interrupts = <0 25 4>;
    clocks = <&clks 212>,
      <&clks 212>,
      <&clks 212>;
    clock-names = "ipg", "ahb", "per";
    bus-width = <4>;
    status = "disabled";
   };

   i2c1: i2c@21a0000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
    reg = <0x021a0000 0x4000>;
    interrupts = <0 36 4>;
    clocks = <&clks 160>;
    status = "disabled";
   };

   i2c2: i2c@21a4000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
    reg = <0x021a4000 0x4000>;
    interrupts = <0 37 4>;
    clocks = <&clks 161>;
    status = "disabled";
   };

   i2c3: i2c@21a8000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
    reg = <0x021a8000 0x4000>;
    interrupts = <0 38 4>;
    clocks = <&clks 162>;
    status = "disabled";
   };

   memory-controller@21b0000 {
    compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
    reg = <0x021b0000 0x4000>;
    clocks = <&clks 180>;
   };

   fec2: ethernet@21b4000 {
    compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
    reg = <0x021b4000 0x4000>;
    interrupt-names = "int0", "pps";
    interrupts = <0 102 4>,
          <0 103 4>;
    clocks = <&clks 172>,
      <&clks 225>,
      <&clks 228>,
      <&clks 231>,
      <&clks 228>;
    clock-names = "ipg", "ahb", "ptp",
           "enet_clk_ref", "enet_out";
    fsl,stop-mode = <&gpr 0x10 4>;
    status = "disabled";
   };

   weim: memory-controller@21b8000 {
    #address-cells = <2>;
    #size-cells = <1>;
    compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
    reg = <0x021b8000 0x4000>;
    interrupts = <0 14 4>;
    clocks = <&clks 213>;
    fsl,weim-cs-gpr = <&gpr>;
    status = "disabled";
   };

   ocotp: efuse@21bc000 {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "fsl,imx6sx-ocotp", "syscon";
    reg = <0x021bc000 0x4000>;
    clocks = <&clks 163>;

    cpu_speed_grade: speed-grade@10 {
     reg = <0x10 4>;
    };

    tempmon_calib: calib@38 {
     reg = <0x38 4>;
    };

    tempmon_temp_grade: temp-grade@20 {
     reg = <0x20 4>;
    };
   };

   sai1: sai@21d4000 {
    compatible = "fsl,imx6sx-sai";
    reg = <0x021d4000 0x4000>;
    interrupts = <0 97 4>;
    clocks = <&clks 237>,
      <&clks 206>,
      <&clks 0>, <&clks 0>;
    clock-names = "bus", "mclk1", "mclk2", "mclk3";
    dma-names = "rx", "tx";
    dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
    status = "disabled";
   };

   audmux: audmux@21d8000 {
    compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
    reg = <0x021d8000 0x4000>;
    status = "disabled";
   };

   sai2: sai@21dc000 {
    compatible = "fsl,imx6sx-sai";
    reg = <0x021dc000 0x4000>;
    interrupts = <0 98 4>;
    clocks = <&clks 238>,
      <&clks 207>,
      <&clks 0>, <&clks 0>;
    clock-names = "bus", "mclk1", "mclk2", "mclk3";
    dma-names = "rx", "tx";
    dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
    status = "disabled";
   };

   qspi1: spi@21e0000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-qspi";
    reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
    reg-names = "QuadSPI", "QuadSPI-memory";
    interrupts = <0 107 4>;
    clocks = <&clks 177>,
      <&clks 177>;
    clock-names = "qspi_en", "qspi";
    status = "disabled";
   };

   qspi2: spi@21e4000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-qspi";
    reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
    reg-names = "QuadSPI", "QuadSPI-memory";
    interrupts = <0 109 4>;
    clocks = <&clks 183>,
      <&clks 183>;
    clock-names = "qspi_en", "qspi";
    status = "disabled";
   };

   uart2: serial@21e8000 {
    compatible = "fsl,imx6sx-uart",
          "fsl,imx6q-uart", "fsl,imx21-uart";
    reg = <0x021e8000 0x4000>;
    interrupts = <0 27 4>;
    clocks = <&clks 204>,
      <&clks 205>;
    clock-names = "ipg", "per";
    dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
    dma-names = "rx", "tx";
    status = "disabled";
   };

   uart3: serial@21ec000 {
    compatible = "fsl,imx6sx-uart",
          "fsl,imx6q-uart", "fsl,imx21-uart";
    reg = <0x021ec000 0x4000>;
    interrupts = <0 28 4>;
    clocks = <&clks 204>,
      <&clks 205>;
    clock-names = "ipg", "per";
    dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
    dma-names = "rx", "tx";
    status = "disabled";
   };

   uart4: serial@21f0000 {
    compatible = "fsl,imx6sx-uart",
          "fsl,imx6q-uart", "fsl,imx21-uart";
    reg = <0x021f0000 0x4000>;
    interrupts = <0 29 4>;
    clocks = <&clks 204>,
      <&clks 205>;
    clock-names = "ipg", "per";
    dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
    dma-names = "rx", "tx";
    status = "disabled";
   };

   uart5: serial@21f4000 {
    compatible = "fsl,imx6sx-uart",
          "fsl,imx6q-uart", "fsl,imx21-uart";
    reg = <0x021f4000 0x4000>;
    interrupts = <0 30 4>;
    clocks = <&clks 204>,
      <&clks 205>;
    clock-names = "ipg", "per";
    dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
    dma-names = "rx", "tx";
    status = "disabled";
   };

   i2c4: i2c@21f8000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
    reg = <0x021f8000 0x4000>;
    interrupts = <0 35 4>;
    clocks = <&clks 217>;
    status = "disabled";
   };
  };

  aips3: bus@2200000 {
   compatible = "fsl,aips-bus", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   reg = <0x02200000 0x100000>;
   ranges;

   spba-bus@2240000 {
    compatible = "fsl,spba-bus", "simple-bus";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x02240000 0x40000>;
    ranges;

    csi1: csi@2214000 {
     reg = <0x02214000 0x4000>;
     interrupts = <0 7 4>;
     clocks = <&clks 173>,
       <&clks 159>,
       <&clks 142>;
     clock-names = "disp-axi", "csi_mclk", "dcic";
     status = "disabled";
    };

    pxp: pxp@2218000 {
     compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
     reg = <0x02218000 0x4000>;
     interrupts = <0 8 4>;
     clocks = <&clks 170>;
     clock-names = "axi";
     power-domains = <&pd_disp>;
     status = "disabled";
    };

    csi2: csi@221c000 {
     reg = <0x0221c000 0x4000>;
     interrupts = <0 41 4>;
     clocks = <&clks 173>,
       <&clks 159>,
       <&clks 143>;
     clock-names = "disp-axi", "csi_mclk", "dcic";
     status = "disabled";
    };

    lcdif1: lcdif@2220000 {
     compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
     reg = <0x02220000 0x4000>;
     interrupts = <0 5 1>;
     clocks = <&clks 175>,
       <&clks 169>,
       <&clks 173>;
     clock-names = "pix", "axi", "disp_axi";
     assigned-clocks = <&clks 71>,
         <&clks 73>;
     assigned-clock-parents = <&clks 34>,
         <&clks 85>;
     power-domains = <&pd_disp>;
     status = "disabled";

     port {
      lcdif1_to_ldb: endpoint {
      };
     };
    };

    lcdif2: lcdif@2224000 {
     compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
     reg = <0x02224000 0x4000>;
     interrupts = <0 6 1>;
     clocks = <&clks 174>,
       <&clks 169>,
       <&clks 173>;
     clock-names = "pix", "axi", "disp_axi";
     power-domains = <&pd_disp>;
     status = "disabled";
    };

    vadc: vadc@2228000 {
     reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
     reg-names = "vadc-vafe", "vadc-vdec";
     clocks = <&clks 215>,
       <&clks 159>;
     clock-names = "vadc", "csi";
     power-domains = <&pd_disp>;
     status = "disabled";
    };
   };

   adc1: adc@2280000 {
    compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
    reg = <0x02280000 0x4000>;
    interrupts = <0 100 4>;
    clocks = <&clks 82>;
    clock-names = "adc";
    fsl,adck-max-frequency = <30000000>, <40000000>,
        <20000000>;
    status = "disabled";
   };

   adc2: adc@2284000 {
    compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
    reg = <0x02284000 0x4000>;
    interrupts = <0 101 4>;
    clocks = <&clks 82>;
    clock-names = "adc";
    fsl,adck-max-frequency = <30000000>, <40000000>,
        <20000000>;
    status = "disabled";
   };

   wdog3: watchdog@2288000 {
    compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
    reg = <0x02288000 0x4000>;
    interrupts = <0 11 4>;
    clocks = <&clks 82>;
    status = "disabled";
   };

   ecspi5: spi@228c000 {
    #address-cells = <1>;
    #size-cells = <0>;
    compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
    reg = <0x0228c000 0x4000>;
    interrupts = <0 18 4>;
    clocks = <&clks 149>,
      <&clks 149>;
    clock-names = "ipg", "per";
    status = "disabled";
   };

   uart6: serial@22a0000 {
    compatible = "fsl,imx6sx-uart",
          "fsl,imx6q-uart", "fsl,imx21-uart";
    reg = <0x022a0000 0x4000>;
    interrupts = <0 17 4>;
    clocks = <&clks 204>,
      <&clks 205>;
    clock-names = "ipg", "per";
    dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
    dma-names = "rx", "tx";
    status = "disabled";
   };

   pwm5: pwm@22a4000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x022a4000 0x4000>;
    interrupts = <0 83 4>;
    clocks = <&clks 218>,
      <&clks 218>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm6: pwm@22a8000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x022a8000 0x4000>;
    interrupts = <0 84 4>;
    clocks = <&clks 219>,
      <&clks 219>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm7: pwm@22ac000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x022ac000 0x4000>;
    interrupts = <0 85 4>;
    clocks = <&clks 220>,
      <&clks 220>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };

   pwm8: pwm@22b0000 {
    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
    reg = <0x022b0000 0x4000>;
    interrupts = <0 86 4>;
    clocks = <&clks 214>,
      <&clks 214>;
    clock-names = "ipg", "per";
    #pwm-cells = <3>;
   };
  };

  pcie: pcie@8ffc000 {
   compatible = "fsl,imx6sx-pcie";
   reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
   reg-names = "dbi", "config";
   #address-cells = <3>;
   #size-cells = <2>;
   device_type = "pci";
   bus-range = <0x00 0xff>;
   ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>,
     <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
   num-lanes = <1>;
   interrupts = <0 120 4>;
   interrupt-names = "msi";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &gpc 0 123 4>,
     <0 0 0 2 &gpc 0 122 4>,
     <0 0 0 3 &gpc 0 121 4>,
     <0 0 0 4 &gpc 0 120 4>;
   clocks = <&clks 182>,
     <&clks 234>,
     <&clks 16>,
     <&clks 173>;
   clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
   power-domains = <&pd_disp>, <&pd_pci>;
   power-domain-names = "pcie", "pcie_phy";
   status = "disabled";
  };
 };
};
# 11 "arch/arm/boot/dts/nxp/imx/javad/javad-imx.dtsi" 2

/ {





 aliases {
  mmc0 = &usdhc4;
  mmc1 = &usdhc3;
  mmc2 = &usdhc2;
  mmc3 = &usdhc1;
 };

 memory@80000000 {
  device_type = "memory";
  reg = <0x80000000 0x40000000>;
 };


 pps-gnss {
  compatible = "pps-gpio";
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_pps>;


  gpios = <&gpio3 25 0>;
  status = "okay";
 };

 regulators {
  compatible = "simple-bus";
  #address-cells = <1>;
  #size-cells = <0>;

  reg_vref_3v3: regulator@2 {
   compatible = "regulator-fixed";
   reg = <1>;
   regulator-name = "vref-3v3";
   regulator-min-microvolt = <3300000>;
   regulator-max-microvolt = <3300000>;
  };
 };

};

&cpu0 {
 operating-points = <

  996000 1250000
  792000 1175000
  396000 1175000
  198000 1175000
  >;
 fsl,soc-operating-points = <

  996000 1250000
  792000 1175000
  396000 1175000
  198000 1175000
 >;
 fsl,arm-soc-shared = <1>;
};

&fec1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_enet1>;
 phy-mode = "rmii";
 phy-handle = <&phy0>;
 max-speed = <100>;
 #clock-cells = <0>;
 clock-frequency = <50000000>;
 phy-reset-gpios = <&gpio5 11 1>;
 phy-reset-duration = <10>;

 status = "okay";
 mdio {
  #address-cells = <1>;
  #size-cells = <0>;

  phy0: ethernet-phy@1 {
   reg = <1>;
  };
 };
};


&usdhc4 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_usdhc4>;

 bus-width = <8>;


 non-removable;
 keep-power-in-suspend;
 status = "okay";
};

&iomuxc {
 pinctrl-names = "default";

 imx6x-sdb {
  pinctrl_usdhc4: usdhc4grp {
   fsl,pins = <
    0x0278 0x05C0 0x0000 0x0 0x0 0x10059
    0x027C 0x05C4 0x0000 0x0 0x0 0x17059
    0x0280 0x05C8 0x0000 0x0 0x0 0x17059
    0x0284 0x05CC 0x0000 0x0 0x0 0x17059
    0x0288 0x05D0 0x0000 0x0 0x0 0x17059
    0x028C 0x05D4 0x0000 0x0 0x0 0x17059
    0x0290 0x05D8 0x0000 0x0 0x0 0x17059
    0x0294 0x05DC 0x0000 0x0 0x0 0x17059
    0x0298 0x05E0 0x0000 0x0 0x0 0x17059
    0x029C 0x05E4 0x0000 0x0 0x0 0x17059
    0x02A0 0x05E8 0x0000 0x0 0x0 0x17068
   >;
  };
 };
};

&adc1 {
    pinctrl-names = "default";
 vref-supply = <&reg_vref_3v3>;
 status = "okay";
};

&adc2 {
    pinctrl-names = "default";
 vref-supply = <&reg_vref_3v3>;
 status = "okay";
};
# 11 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre.dtsi" 2

/ {
 compatible = "javad,imx6sx", "fsl,imx6sx";

 chosen {
  stdout-path = &uart1;
 };


 gpio-poweroff {
  compatible = "gpio-poweroff";
  gpios = <&gpio6 7 0>;
  status = "okay";
 };

 regulators {
  compatible = "simple-bus";
  #address-cells = <1>;
  #size-cells = <0>;

  reg_usb_otg1_vbus: regulator@0 {
   compatible = "regulator-fixed";
   reg = <0>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_usb_otg1>;
   regulator-name = "usb_otg1_vbus";
   regulator-min-microvolt = <5000000>;
   regulator-max-microvolt = <5000000>;
   gpio = <&gpio4 18 0>;
   enable-active-high;
  };
 };
};

&uart1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart1>;
 dma-names = "";
 uart-has-rtscts;
 status = "okay";
};

&uart2 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart2>;

 dma-names = "";
 status = "okay";
};

&uart3 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart3>;

 dma-names = "";
 status = "okay";
};

&uart4 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart4>;
 uart-has-rtscts;
 dma-names = "";
 status = "okay";
};

&uart5 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart5>;
 uart-has-rtscts;
 dma-names = "";
 status = "okay";
};

&uart6 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart6>;
 uart-has-rtscts;
 dma-names = "";
 status = "okay";
};

&flexcan1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_flexcan1>;
 status = "okay";
};

&flexcan2 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_flexcan2>;
 status = "okay";
};

&i2c1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_i2c1>;
 status = "okay";
 clock-frequency = <400000>;

};

&usbphy1 {
    tx-d-cal = <0x5>;
    status = "okay";
};

&usbotg1 {
 vbus-supply = <&reg_usb_otg1_vbus>;
    pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_usb_otg1_id>;
    disable-over-current;
    srp-disable;
    hnp-disable;
    adp-disable;
    status = "okay";
};

&iomuxc {
 pinctrl-names = "default";

 imx6x-sdb {
  pinctrl_uart1: uart1grp {
   fsl,pins = <
    0x0098 0x03E0 0x0000 0x3 0x0 0x1b0b1
    0x0094 0x03DC 0x0830 0x3 0x2 0x1b0b1
    0x00A0 0x03E8 0x0000 0x3 0x0 0x1b0b1
    0x009C 0x03E4 0x082C 0x3 0x2 0x1b0b1
   >;
  };

  pinctrl_uart2: uart2grp {
   fsl,pins = <
    0x0030 0x0378 0x0838 0x0 0x1 0x1b0b1
    0x002C 0x0374 0x0000 0x0 0x0 0x1b0b1


   >;
  };

  pinctrl_uart3: uart3grp {
   fsl,pins = <
    0x01B4 0x04FC 0x0840 0x1 0x4 0x1b0b1
    0x01B8 0x0500 0x0000 0x1 0x0 0x1b0b1
   >;
  };

  pinctrl_uart4: uart4grp {
   fsl,pins = <
    0x0264 0x05AC 0x0848 0x1 0x1 0x1b0b1
    0x0254 0x059C 0x0000 0x1 0x0 0x1b0b1
    0x0250 0x0598 0x0000 0x1 0x0 0x1b0b1
    0x0260 0x05A8 0x0844 0x1 0x1 0x1b0b1
   >;
  };

  pinctrl_uart5: uart5grp {
   fsl,pins = <
    0x00C4 0x040C 0x0850 0x2 0x3 0x1b0b1
    0x00B0 0x03F8 0x0000 0x2 0x0 0x1b0b1
    0x00C0 0x0408 0x0000 0x2 0x0 0x1b0b1
    0x00AC 0x03F4 0x084C 0x2 0x2 0x1b0b1
   >;
  };

  pinctrl_uart6: uart6grp {
   fsl,pins = <
    0x00BC 0x0404 0x0858 0x2 0x3 0x1b0b1
    0x00A8 0x03F0 0x0000 0x2 0x0 0x1b0b1
    0x00B8 0x0400 0x0000 0x2 0x0 0x1b0b1
    0x00A4 0x03EC 0x0854 0x2 0x2 0x1b0b1
   >;
  };

  pinctrl_flexcan1: flexcan1grp-1 {
   fsl,pins = <
    0x026C 0x05B4 0x0000 0x1 0x0 0x1b020
    0x0274 0x05BC 0x068C 0x1 0x0 0x1b020
   >;
  };

  pinctrl_flexcan2: flexcan2grp-1 {
   fsl,pins = <
    0x0268 0x05B0 0x0690 0x1 0x0 0x1b020
    0x0270 0x05B8 0x0000 0x1 0x0 0x1b020
   >;
  };

  pinctrl_i2c1: i2c1grp {
   fsl,pins = <
    0x0014 0x035C 0x07A8 0x0 0x1 0x4001b8b1
    0x0018 0x0360 0x07AC 0x0 0x1 0x4001b8b1
   >;
  };

  pinctrl_usb_otg1: usbotg1grp {
   fsl,pins = <
    0x0188 0x04D0 0x0000 0x5 0x0 0x1b0b0
   >;
  };

  pinctrl_usb_otg1_id: usbotg1idgrp {
   fsl,pins = <
    0x018C 0x04D4 0x0860 0x1 0x2 0x1b0b0
    0x0184 0x04CC 0x0624 0x1 0x2 0x1b0b0
   >;
  };

  pinctrl_pps: ppsgrp {
   fsl,pins = <
    0x0130 0x0478 0x0000 0x5 0x0 0x1b0b1
   >;
  };







 };
};
# 11 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre_3s.dtsi" 2
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth-dp.dtsi" 1
# 13 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth-dp.dtsi"
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth.dtsi" 1
# 45 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth.dtsi"
&iomuxc {
 pinctrl-names = "default";
 imx6x-sdb {
  pinctrl_enet1: enet1grp {
   fsl,pins = <
    0x0088 0x03D0 0x0764 0x0 0x1 0xf0a9
    0x0084 0x03CC 0x0000 0x0 0x0 0xb0a9
# 72 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth.dtsi"
    0x01D8 0x0520 0x0000 0x0 0x0 0xb0a9
    0x01DC 0x0524 0x0000 0x0 0x0 0xb0a9
    0x01E8 0x0530 0x0000 0x0 0x0 0xb0a9
    0x01D4 0x051C 0x0000 0x1 0x0 0x3081
    0x01C0 0x0508 0x0000 0x0 0x0 0x3081
    0x01C4 0x050C 0x0000 0x0 0x0 0x3081
    0x01D0 0x0518 0x0000 0x0 0x0 0x3081
    0x0090 0x03D8 0x0760 0x1 0x1 0x0091
    0x01EC 0x0534 0x0000 0x5 0x0 0xb0b0





   >;
  };
 };
};
# 14 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-eth-dp.dtsi" 2
# 12 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre_3s.dtsi" 2

/ {
 model = "JAVAD TRE-3S";
 compatible = "javad,tre-3s", "javad,imx6sx", "fsl,imx6sx";
};
# 13 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-01-03-tre_3s.dts" 2
# 1 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre-usb2.dtsi" 1
# 10 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-tre-usb2.dtsi"
/ {
 regulators {
  compatible = "simple-bus";
  #address-cells = <1>;
  #size-cells = <0>;

  reg_usb_otg2_vbus: regulator@1 {
   compatible = "regulator-fixed";
   reg = <0>;
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_usb_otg2>;
   regulator-name = "usb_otg2_vbus";
   regulator-min-microvolt = <5000000>;
   regulator-max-microvolt = <5000000>;
   gpio = <&gpio4 22 0>;
   enable-active-high;
  };
 };
};

&usbphy2 {
    tx-d-cal = <0x5>;
    status = "okay";
};

&usbotg2 {
 vbus-supply = <&reg_usb_otg2_vbus>;
    pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_usb_otg2_id>;
    disable-over-current;
    srp-disable;
    hnp-disable;
    adp-disable;
 dr_mode = "otg";
    status = "okay";
};

&iomuxc {
 pinctrl-names = "default";

 imx6x-sdb {

  pinctrl_usb_otg2: usbotg2grp {
   fsl,pins = <
    0x0198 0x04E0 0x0000 0x5 0x0 0x1b0b0
   >;
  };

  pinctrl_usb_otg2_id: usbotg2idgrp {
   fsl,pins = <
    0x0180 0x04C8 0x085C 0x1 0x2 0x1b0b0
    0x0194 0x04DC 0x0628 0x1 0x2 0x1b0b0
   >;
  };
 };
};
# 14 "arch/arm/boot/dts/nxp/imx/javad/javad-imx-01-03-tre_3s.dts" 2