linux-kernel - Re: [PATCH] phy: exynos5-usbdrd: fix clock prepare imbalance

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Message-ID: <CAPLW+4mT+BcK+sLTenaNP7T3iFF1yXj4kziSYiJx2gOYV2NSWg@mail.gmail.com>
Date: Tue, 7 Oct 2025 14:20:03 -0500
From: Sam Protsenko <semen.protsenko@...aro.org>
To: André Draszik <andre.draszik@...aro.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, 
	Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>, 
	Peter Griffin <peter.griffin@...aro.org>, Tudor Ambarus <tudor.ambarus@...aro.org>, 
	Will McVicker <willmcvicker@...gle.com>, kernel-team@...roid.com, 
	linux-phy@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	stable@...r.kernel.org
Subject: Re: [PATCH] phy: exynos5-usbdrd: fix clock prepare imbalance

On Mon, Oct 6, 2025 at 3:07 AM André Draszik <andre.draszik@...aro.org> wrote:
>
> Commit f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend
> with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the
> inverse of clk_bulk_prepare_enable() while it should have of course
> used clk_bulk_disable_unprepare(). This means incorrect reference
> counts to the CMU driver remain.
>
> Update the code accordingly.
>
> Fixes: f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)")
> CC: stable@...r.kernel.org
> Signed-off-by: André Draszik <andre.draszik@...aro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>

>  drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index a88ba95bdc8f539dd8d908960ee2079905688622..1c8bf80119f11e2cd2f07c829986908c150688ac 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -1823,7 +1823,7 @@ static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw,
>                 phy_drd->orientation = orientation;
>         }
>
> -       clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks);
> +       clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
>
>         return 0;
>  }
>
> ---
> base-commit: 3b9b1f8df454caa453c7fb07689064edb2eda90a
> change-id: 20251006-gs101-usb-phy-clk-imbalance-62eb4e761d55
>
> Best regards,
> --
> André Draszik <andre.draszik@...aro.org>
>
>