linux-kernel - Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller

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Message-ID: <4rghtk5qv4u7vx4nogctquu3skvxis4npxfukgtqeilbofyclr@nhkrkojv3syh>
Date: Tue, 7 Oct 2025 15:28:55 -0700
From: Manivannan Sadhasivam <mani@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>
Cc: Vincent Guittot <vincent.guittot@...aro.org>, chester62515@...il.com, 
	mbrugger@...e.com, ghennadi.procopciuc@....nxp.com, s32@....com, 
	bhelgaas@...gle.com, jingoohan1@...il.com, kwilczynski@...nel.org, robh@...nel.org, 
	krzk+dt@...nel.org, conor+dt@...nel.org, Ionut.Vicovan@....com, 
	larisa.grigore@....com, Ghennadi.Procopciuc@....com, ciprianmarian.costea@....com, 
	bogdan.hamciuc@....com, Frank.li@....com, linux-arm-kernel@...ts.infradead.org, 
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	imx@...ts.linux.dev, cassel@...nel.org
Subject: Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller

On Tue, Oct 07, 2025 at 05:41:55PM +0200, Lorenzo Pieralisi wrote:
> On Mon, Sep 22, 2025 at 11:51:07AM +0530, Manivannan Sadhasivam wrote:
> 
> [...]
> 
> > > +                  /*
> > > +                   * non-prefetchable memory, with best case size and
> > > +                   * alignment
> > > +                   */
> > > +                  <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>;
> > 
> > s/0x82000000/0x02000000
> > 
> > And the PCI address really starts from 0x00000000? I don't think so.
> 
> Isn't the DWC ATU programmed to make sure that the PCI memory window DT
> provides _is_ the PCI "bus" memory base address ?
> 
> It is a question, I don't know the DWC inner details fully.
> 
> I don't get what you mean by "I don't think so". Either the host controller
> AXI<->PCI translation is programmable, then the PCI base address is what
> we decide it is or it isn't.
> 

As per the binding, I/O PCI address already starts from 0x0. How can you have
two OB mappings with same PCI address?

- Mani

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