linux-kernel - [tip: irq/urgent] irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resume

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Message-ID: <175982566785.709179.17178660704346674375.tip-bot2@tip-bot2>
Date: Tue, 07 Oct 2025 08:27:47 -0000
From: "tip-bot2 for Lucas Zampieri" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Jia Wang <wangjia@...rarisc.com>, Charles Mirabile <cmirabil@...hat.com>,
 Lucas Zampieri <lzampier@...hat.com>, Thomas Gleixner <tglx@...utronix.de>,
 x86@...nel.org, linux-kernel@...r.kernel.org, maz@...nel.org
Subject: [tip: irq/urgent] irqchip/sifive-plic: Avoid interrupt ID 0 handling
 during suspend/resume

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     f75e07bf5226da640fa99a0594687c780d9bace4
Gitweb:        https://git.kernel.org/tip/f75e07bf5226da640fa99a0594687c780d9bace4
Author:        Lucas Zampieri <lzampier@...hat.com>
AuthorDate:    Tue, 23 Sep 2025 15:43:19 +01:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Tue, 07 Oct 2025 10:23:22 +02:00

irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resume

According to the PLIC specification[1], global interrupt sources are
assigned small unsigned integer identifiers beginning at the value 1.
An interrupt ID of 0 is reserved to mean "no interrupt".

The current plic_irq_resume() and plic_irq_suspend() functions incorrectly
start the loop from index 0, which accesses the register space for the
reserved interrupt ID 0.

Change the loop to start from index 1, skipping the reserved
interrupt ID 0 as per the PLIC specification.

This prevents potential undefined behavior when accessing the reserved
register space during suspend/resume cycles.

Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Co-developed-by: Jia Wang <wangjia@...rarisc.com>
Signed-off-by: Jia Wang <wangjia@...rarisc.com>
Co-developed-by: Charles Mirabile <cmirabil@...hat.com>
Signed-off-by: Charles Mirabile <cmirabil@...hat.com>
Signed-off-by: Lucas Zampieri <lzampier@...hat.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Link: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0
---
 drivers/irqchip/irq-sifive-plic.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 559fda8..cbd7697 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -254,7 +254,8 @@ static int plic_irq_suspend(void)
 
 	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;
 
-	for (i = 0; i < priv->nr_irqs; i++) {
+	/* irq ID 0 is reserved */
+	for (i = 1; i < priv->nr_irqs; i++) {
 		__assign_bit(i, priv->prio_save,
 			     readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID));
 	}
@@ -285,7 +286,8 @@ static void plic_irq_resume(void)
 
 	priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv;
 
-	for (i = 0; i < priv->nr_irqs; i++) {
+	/* irq ID 0 is reserved */
+	for (i = 1; i < priv->nr_irqs; i++) {
 		index = BIT_WORD(i);
 		writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0,
 		       priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID);