lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <15c23554-b51e-4656-81bc-a890c8c989a9@kernel.org>
Date: Tue, 7 Oct 2025 17:39:20 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Sven Püschel <s.pueschel@...gutronix.de>,
 Jacob Chen <jacob-chen@...wrt.com>,
 Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
 Mauro Carvalho Chehab <mchehab@...nel.org>, Heiko Stuebner
 <heiko@...ech.de>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, kernel@...gutronix.de
Subject: Re: [PATCH 15/16] arm64: dts: rockchip: increase rga3 clock speed

On 07/10/2025 17:32, Sven Püschel wrote:
> Increase the RGA3 clock speed to get the maximal possible frames
> per second. By default the core and axi clock is set to 375Mhz.
> 
> Signed-off-by: Sven Püschel <s.pueschel@...gutronix.de>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 08885d9c19e0c104ab0f723ec161b83998cfb9c7..57e320267bb629893bb884bf4e8d6bbc22f8d628 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -1179,6 +1179,8 @@ rga3_core0: rga@...60000 {
>  		interrupt-names = "rga3_core0_irq";
>  		clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>;
>  		clock-names = "aclk", "hclk", "sclk";
> +		assigned-clocks = <&cru CLK_RGA3_0_CORE>, <&cru ACLK_RGA3_0>;
> +		assigned-clock-rates = <800000000>, <800000000>;

You just added these nodes, so this must be squashed. Do not add
incomplete code which immediately you fix.

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ