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Message-Id: <20251007140434.606051-7-kamal.dasu@broadcom.com>
Date: Tue, 7 Oct 2025 10:04:34 -0400
From: Kamal Dasu <kamal.dasu@...adcom.com>
To: andersson@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
florian.fainelli@...adcom.com,
ulf.hansson@...aro.org,
adrian.hunter@...el.com
Cc: bcm-kernel-feedback-list@...adcom.com,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org,
Kamal Dasu <kamal.dasu@...adcom.com>
Subject: [PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM
Added support to save and restore registers that are critical
during PM.
Signed-off-by: Kamal Dasu <kamal.dasu@...adcom.com>
---
drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++--
1 file changed, 107 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
index 42709ca8111d..7de395c86f2f 100644
--- a/drivers/mmc/host/sdhci-brcmstb.c
+++ b/drivers/mmc/host/sdhci-brcmstb.c
@@ -38,28 +38,109 @@
#define SDIO_CFG_OP_DLY_DEFAULT 0x80000003
#define SDIO_CFG_CQ_CAPABILITY 0x4c
#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12)
+#define SDIO_CFG_SD_PIN_SEL 0x44
+#define SDIO_CFG_V1_SD_PIN_SEL 0x54
+#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C
#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac
#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0)
+#define SDIO_BOOT_MAIN_CTL 0x0
+
#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
/* Select all SD UHS type I SDR speed above 50MB/s */
#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
-struct sdhci_brcmstb_priv {
- void __iomem *cfg_regs;
- unsigned int flags;
- struct clk *base_clk;
- u32 base_freq_hz;
+enum cfg_core_ver {
+ SDIO_CFG_CORE_V1 = 1,
+ SDIO_CFG_CORE_V2,
+};
+
+struct sdhci_brcmstb_saved_regs {
+ u32 sd_pin_sel;
+ u32 phy_sw_mode0_rxctrl;
+ u32 max_50mhz_mode;
+ u32 boot_main_ctl;
};
struct brcmstb_match_priv {
void (*cfginit)(struct sdhci_host *host);
void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
+ void (*save_restore_regs)(struct mmc_host *mmc, int save);
struct sdhci_ops *ops;
const unsigned int flags;
};
+struct sdhci_brcmstb_priv {
+ void __iomem *cfg_regs;
+ void __iomem *boot_regs;
+ struct sdhci_brcmstb_saved_regs saved_regs;
+ unsigned int flags;
+ struct clk *base_clk;
+ u32 base_freq_hz;
+ const struct brcmstb_match_priv *match_priv;
+};
+
+static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+ void __iomem *cr = priv->cfg_regs;
+ bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+ if (is_emmc && priv->boot_regs)
+ sr->boot_main_ctl = readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+ if (ver == SDIO_CFG_CORE_V1) {
+ sr->sd_pin_sel = readl(cr + SDIO_CFG_V1_SD_PIN_SEL);
+ return;
+ }
+
+ sr->sd_pin_sel = readl(cr + SDIO_CFG_SD_PIN_SEL);
+ sr->phy_sw_mode0_rxctrl = readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+ sr->max_50mhz_mode = readl(cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver ver)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct sdhci_brcmstb_saved_regs *sr = &priv->saved_regs;
+ void __iomem *cr = priv->cfg_regs;
+ bool is_emmc = mmc->caps & MMC_CAP_NONREMOVABLE;
+
+ if (is_emmc && priv->boot_regs)
+ writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
+
+ if (ver == SDIO_CFG_CORE_V1) {
+ writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+ return;
+ }
+
+ writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
+ writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
+ writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int save)
+{
+ if (save)
+ sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1);
+ else
+ sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1);
+}
+
+static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int save)
+{
+ if (save)
+ sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2);
+ else
+ sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2);
+}
+
static inline void enable_clock_gating(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 = {
static struct brcmstb_match_priv match_priv_7445 = {
.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+ .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
.ops = &sdhci_brcmstb_ops,
};
static struct brcmstb_match_priv match_priv_72116 = {
.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
+ .save_restore_regs = sdhci_brcmstb_save_restore_regs_v1,
.ops = &sdhci_brcmstb_ops_72116,
};
static const struct brcmstb_match_priv match_priv_7216 = {
.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+ .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
.hs400es = sdhci_brcmstb_hs400es,
.ops = &sdhci_brcmstb_ops_7216,
};
static struct brcmstb_match_priv match_priv_74165b0 = {
.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
+ .save_restore_regs = sdhci_brcmstb_save_restore_regs_v2,
.hs400es = sdhci_brcmstb_hs400es,
.ops = &sdhci_brcmstb_ops_74165b0,
};
@@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
pltfm_host = sdhci_priv(host);
priv = sdhci_pltfm_priv(pltfm_host);
+ priv->match_priv = match->data;
if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
@@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev)
if (res)
goto err;
+ /* map non-standard BOOT registers if present */
+ if (host->mmc->caps & MMC_CAP_NONREMOVABLE) {
+ priv->boot_regs = devm_platform_get_and_ioremap_resource(pdev, 2, NULL);
+ if (IS_ERR(priv->boot_regs))
+ priv->boot_regs = NULL;
+ }
+
/*
* Automatic clock gating does not work for SD cards that may
* voltage switch so only enable it for non-removable devices.
@@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev)
struct sdhci_host *host = dev_get_drvdata(dev);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ const struct brcmstb_match_priv *match_priv = priv->match_priv;
+
int ret;
+ if (match_priv->save_restore_regs)
+ match_priv->save_restore_regs(host->mmc, 1);
+
clk_disable_unprepare(priv->base_clk);
if (host->mmc->caps2 & MMC_CAP2_CQE) {
ret = cqhci_suspend(host->mmc);
@@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev)
struct sdhci_host *host = dev_get_drvdata(dev);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ const struct brcmstb_match_priv *match_priv = priv->match_priv;
int ret;
ret = sdhci_pltfm_resume(dev);
@@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev)
ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
}
+ if (match_priv->save_restore_regs)
+ match_priv->save_restore_regs(host->mmc, 0);
+
if (host->mmc->caps2 & MMC_CAP2_CQE)
ret = cqhci_resume(host->mmc);
--
2.34.1
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