linux-kernel - Re: [PATCH] mtd: spi-nor: Enable locking for n25q00a

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4888cefa-e8be-4f0d-9d4a-c82f9ff6cda0@linux.dev>
Date: Tue, 7 Oct 2025 10:20:01 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Pratyush Yadav <pratyush@...nel.org>
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>,
 Michael Walle <mwalle@...nel.org>, linux-mtd@...ts.infradead.org,
 Richard Weinberger <richard@....at>, linux-kernel@...r.kernel.org,
 Miquel Raynal <miquel.raynal@...tlin.com>,
 Vignesh Raghavendra <vigneshr@...com>
Subject: Re: [PATCH] mtd: spi-nor: Enable locking for n25q00a

On 10/7/25 09:15, Pratyush Yadav wrote:
> On Mon, Oct 06 2025, Sean Anderson wrote:
> 
>> The datasheet for n25q00a shows that the status register has the same
>> layout as for n25q00, so use the same flags to enable locking support.
>> These flags should have been added back in commit 150ccc181588 ("mtd:
>> spi-nor: Enable locking for n25q128a11"), but they were removed by the
>> maintainer...
> 
> This makes it sound like the maintainer did something wrong, which is
> not true. Tudor had a good reason for removing them.

I disagree. The maintainer used his position of authority to make the
submitter second-guess their correct patch.

These flashes have capacity of greater than the 8 MiB that can be
protected using 3 BP bits. Micron (and ST before them?) addressed this
by adding a fourth BP bit. This is consistent across every flash in this
series, and is clearly documented in every datasheet. Defaulting to 3
bits is buggy behavior: we should assume flashes behave per their
datasheets until proven otherwise, especially for less-popular features
that the original submitter may not have tested.

The original patch was entirely correct, and the maintainer's
justification for removing the second hunk is flawed.

> Jungseung did not
> have the flash at hand and Tudor didn't want to apply patches that
> weren't tested. Both were in agreement for removing the n25q00a changes.
> 
> If you are going to mention that commit, then mention the full context,
> and then also mention what has changed since that makes it possible to
> add those changes back in. Having tested them on the real hardware for
> example.
> 
>>
>> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
>> ---
>> Tested with a mt25qu01gbbb, which shares the same flash ID.
> 
> Ughh, is this another case of flash ID reuse? Do mt25qu and n25q00a
> flashes behave exactly the same and only have two names? If not, then
> how do you know if n25q00a will also work with these changes?

I examined the datasheet for the n25q00a and determined that it has the
same status register layout.

In fact, every n25q and mt25q flash has the same status register layout,
which (as noted above) is necessary to support capacities greater than 8
MiB (and all flashes in this series have such capacity).

--Sea

>>
>>  drivers/mtd/spi-nor/micron-st.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
>> index 187239ccd549..17c7d6322508 100644
>> --- a/drivers/mtd/spi-nor/micron-st.c
>> +++ b/drivers/mtd/spi-nor/micron-st.c
>> @@ -486,6 +486,8 @@ static const struct flash_info st_nor_parts[] = {
>>  		.id = SNOR_ID(0x20, 0xbb, 0x21),
>>  		.name = "n25q00a",
>>  		.size = SZ_128M,
>> +		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
>> +			 SPI_NOR_BP3_SR_BIT6,
>>  		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
>>  		.mfr_flags = USE_FSR,
>>  		.fixups = &n25q00_fixups,
>