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Message-ID: <20251008-canopener-marsupial-a92355b656ef@spud>
Date: Wed, 8 Oct 2025 22:21:06 +0100
From: Conor Dooley <conor@...nel.org>
To: Svyatoslav Ryhel <clamor95@...il.com>
Cc: Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Sowjanya Komatineni <skomatineni@...dia.com>,
Luca Ceresoli <luca.ceresoli@...tlin.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Mikko Perttunen <mperttunen@...dia.com>,
Linus Walleij <linus.walleij@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jonas Schwöbel <jonasschwoebel@...oo.de>,
Dmitry Osipenko <digetx@...il.com>,
Charan Pedumuru <charan.pedumuru@...il.com>,
Diogo Ivo <diogo.ivo@...nico.ulisboa.pt>,
Aaron Kling <webgeek1234@...il.com>, Arnd Bergmann <arnd@...db.de>,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org, linux-clk@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-staging@...ts.linux.dev
Subject: Re: [PATCH v4 22/24] dt-bindings: display: tegra: document Tegra20
and Tegra30 CSI
On Wed, Oct 08, 2025 at 10:30:44AM +0300, Svyatoslav Ryhel wrote:
> Document CSI HW block found in Tegra20 and Tegra30 SoC.
>
> The #nvidia,mipi-calibrate-cells is not an introduction of property, such
> property already exists in nvidia,tegra114-mipi.yaml and is used in
> multiple device trees. In case of Tegra30 and Tegra20 CSI block combines
> mipi calibration function and CSI function, in Tegra114+ mipi calibration
> got a dedicated hardware block which is already supported. This property
> here is used to align with mipi-calibration logic used by Tegra114+.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> ---
> .../display/tegra/nvidia,tegra20-csi.yaml | 135 ++++++++++++++++++
> 1 file changed, 135 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> new file mode 100644
> index 000000000000..817b3097846b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra20 CSI controller
> +
> +maintainers:
> + - Svyatoslav Ryhel <clamor95@...il.com>
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra20-csi
> + - nvidia,tegra30-csi
> +
> + reg:
> + maxItems: 1
> +
> + clocks: true
> + clock-names: true
> +
> + avdd-dsi-csi-supply:
> + description: DSI/CSI power supply. Must supply 1.2 V.
> +
> + power-domains:
> + maxItems: 1
> +
> + "#nvidia,mipi-calibrate-cells":
> + description:
> + The number of cells in a MIPI calibration specifier. Should be 1.
> + The single cell specifies an id of the pad that need to be
> + calibrated for a given device. Valid pad ids for receiver would be
> + 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + const: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^channel@[0-1]$":
> + type: object
> + description: channel 0 represents CSI-A and 1 represents CSI-B
> + additionalProperties: false
> +
> + properties:
> + reg:
> + maximum: 1
> +
> + nvidia,mipi-calibrate:
> + description: Should contain a phandle and a specifier specifying
> + which pad is used by this CSI channel and needs to be calibrated.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: port receiving the video stream from the sensor
> +
> + properties:
> + endpoint:
> + $ref: /schemas/media/video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + required:
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: port sending the video stream to the VI
> +
> + required:
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - port@0
> + - port@1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra20-csi
> + then:
> + properties:
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra30-csi
> + then:
> + properties:
> + clocks:
> + items:
> + - description: module clock
> + - description: PAD A clock
> + - description: PAD B clock
> +
> + clock-names:
> + items:
> + - const: csi
> + - const: csia-pad
> + - const: csib-pad
This clocks section seems like it could get simpler. Since the clock
descriptions are shared, and tegra20 has no clock-names, you could just
move the detail of the properties out to where you have the ": true"
stuff (we prefer that properties are defined outside of if/then/else
blocks) and just restrict them here. For tegra20 that'd be
if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-csi
then:
properties:
clocks:
maxItems: 1
clock-names: false
(although it could easily be maxItems: 1 ?)
and for tegra30
if:
properties:
compatible:
contains:
enum:
- nvidia,tegra30-csi
then:
properties:
clocks:
minItems: 3
clock-names:
maxItems: 3
Of course you'd then have to add minItems: 1 and maxItems: 3 to the
extracted definitions.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> + - "#address-cells"
> + - "#size-cells"
> +
> +# see nvidia,tegra20-vi.yaml for an example
> --
> 2.48.1
>
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