linux-kernel - Re: [PATCH v5] ASoC: wm8978: add missing BCLK divider setup

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Message-ID: <72ca91be-e953-428b-8314-d32de3478bc0@sirena.org.uk>
Date: Wed, 8 Oct 2025 22:44:41 +0100
From: Mark Brown <broonie@...nel.org>
To: Sune Brian <briansune@...il.com>
Cc: Charles Keepax <ckeepax@...nsource.cirrus.com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
	linux-sound@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5] ASoC: wm8978: add missing BCLK divider setup

On Thu, Oct 09, 2025 at 05:27:58AM +0800, Sune Brian wrote:
> Mark Brown <broonie@...nel.org> 於 2025年10月9日 週四 上午4:26寫道：

> > Another one I've seen is that you're using the BCLK as the MCLK for
> > another part (a few devices even require this), you might want to run
> > BCLK at 256fs or whatever for the MCLK even though it's not needed for
> > when used as BCLK.

> If you need BCLK as MCLK same clock rate why you need to use BCLK from
> first place?

This is often partly a pinmuxing/routing question - if the CODEC is the
clock provider (and perhaps you're using a CODEC PLL so the clock isn't
visible without being output by the CODEC) then using a fast BCLK can
either be needed due to a lack of other places to output the MCLK or
just seem convenient to the board designer due to where the available
pins are.

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