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Message-ID: <20251008064905.702582-1-kkartik@nvidia.com>
Date: Wed, 8 Oct 2025 12:19:05 +0530
From: Kartik Rajput <kkartik@...dia.com>
To: <linus.walleij@...aro.org>, <brgl@...ev.pl>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <linux-kernel@...r.kernel.org>,
<linux-gpio@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<devicetree@...r.kernel.org>
CC: Prathamesh Shete <pshete@...dia.com>, Nathan Hartman
<nhartman@...dia.com>, Kartik Rajput <kkartik@...dia.com>
Subject: [PATCH v2] gpio: tegra186: Add support for Tegra410
From: Prathamesh Shete <pshete@...dia.com>
Extend the existing Tegra186 GPIO controller driver with support for
the GPIO controller found on Tegra410. Tegra410 supports two GPIO
controllers referred to as 'COMPUTE' and 'SYSTEM'.
Co-developed-by: Nathan Hartman <nhartman@...dia.com>
Signed-off-by: Nathan Hartman <nhartman@...dia.com>
Signed-off-by: Prathamesh Shete <pshete@...dia.com>
Signed-off-by: Kartik Rajput <kkartik@...dia.com>
---
v1 -> v2:
* Move Tegra410 GPIO Ports definition to gpio-tegra186.c
* Rename Tegra410 Main GPIO as System GPIO.
* Add Compute GPIOs.
* Update ACPI IDs.
* Set instance ID as 0 for SYSTEM and COMPUTE GPIOs.
* Added Nathan as co-author for adding compute GPIO support
and renaming MAIN GPIOs as SYSTEM GPIOs.
---
drivers/gpio/gpio-tegra186.c | 90 +++++++++++++++++++++++++++++++++++-
1 file changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index 4d3db6e06eeb..0485a7b98347 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2016-2022 NVIDIA Corporation
+ * Copyright (c) 2016-2025 NVIDIA Corporation
*
* Author: Thierry Reding <treding@...dia.com>
* Dipen Patel <dpatel@...dia.com>
@@ -69,6 +69,36 @@
#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
+/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */
+#define TEGRA410_COMPUTE_GPIO_PORT_A 0
+#define TEGRA410_COMPUTE_GPIO_PORT_B 1
+#define TEGRA410_COMPUTE_GPIO_PORT_C 2
+#define TEGRA410_COMPUTE_GPIO_PORT_D 3
+#define TEGRA410_COMPUTE_GPIO_PORT_E 4
+
+#define TEGRA410_COMPUTE_GPIO(port, offset) \
+ ((TEGRA410_COMPUTE_GPIO_PORT_##port * 8) + (offset))
+
+/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */
+#define TEGRA410_SYSTEM_GPIO_PORT_A 0
+#define TEGRA410_SYSTEM_GPIO_PORT_B 1
+#define TEGRA410_SYSTEM_GPIO_PORT_C 2
+#define TEGRA410_SYSTEM_GPIO_PORT_D 3
+#define TEGRA410_SYSTEM_GPIO_PORT_E 4
+#define TEGRA410_SYSTEM_GPIO_PORT_I 5
+#define TEGRA410_SYSTEM_GPIO_PORT_J 6
+#define TEGRA410_SYSTEM_GPIO_PORT_K 7
+#define TEGRA410_SYSTEM_GPIO_PORT_L 8
+#define TEGRA410_SYSTEM_GPIO_PORT_M 9
+#define TEGRA410_SYSTEM_GPIO_PORT_N 10
+#define TEGRA410_SYSTEM_GPIO_PORT_P 11
+#define TEGRA410_SYSTEM_GPIO_PORT_Q 12
+#define TEGRA410_SYSTEM_GPIO_PORT_R 13
+#define TEGRA410_SYSTEM_GPIO_PORT_V 14
+
+#define TEGRA410_SYSTEM_GPIO(port, offset) \
+ ((TEGRA410_SYSTEM_GPIO_PORT_##port * 8) + (offset))
+
struct tegra_gpio_port {
const char *name;
unsigned int bank;
@@ -1304,6 +1334,62 @@ static const struct tegra_gpio_soc tegra256_main_soc = {
.has_vm_support = true,
};
+#define TEGRA410_GPIO_PORT(_die, _name, _bank, _port, _pins) \
+ [TEGRA410_##_die##_GPIO_PORT_##_name] = { \
+ .name = "_" #_die "_" #_name, \
+ .bank = _bank, \
+ .port = _port, \
+ .pins = _pins, \
+ }
+
+#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \
+ TEGRA410_GPIO_PORT(COMPUTE, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra410_compute_ports[] = {
+ TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3),
+ TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8),
+ TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3),
+ TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8),
+ TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8),
+};
+
+static const struct tegra_gpio_soc tegra410_compute_soc = {
+ .num_ports = ARRAY_SIZE(tegra410_compute_ports),
+ .ports = tegra410_compute_ports,
+ .name = "tegra410-gpio-compute",
+ .num_irqs_per_bank = 8,
+ .instance = 0,
+};
+
+#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \
+ TEGRA410_GPIO_PORT(SYSTEM, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra410_system_ports[] = {
+ TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7),
+ TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8),
+ TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8),
+ TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8),
+ TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6),
+ TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8),
+ TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7),
+ TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7),
+ TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7),
+ TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7),
+ TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6),
+ TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8),
+ TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3),
+ TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2),
+ TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2),
+};
+
+static const struct tegra_gpio_soc tegra410_system_soc = {
+ .num_ports = ARRAY_SIZE(tegra410_system_ports),
+ .ports = tegra410_system_ports,
+ .name = "tegra410-gpio-system",
+ .num_irqs_per_bank = 8,
+ .instance = 0,
+};
+
static const struct of_device_id tegra186_gpio_of_match[] = {
{
.compatible = "nvidia,tegra186-gpio",
@@ -1339,6 +1425,8 @@ static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
{ .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
{ .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
{ .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
+ { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc },
+ { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc },
{}
};
MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
--
2.43.0
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