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Message-ID: <aa06df81-e594-469a-85ee-9dd1e192e2f4@oss.qualcomm.com>
Date: Wed, 8 Oct 2025 13:35:53 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Md Sadre Alam <quic_mdalam@...cinc.com>, broonie@...nel.org,
        robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
        andersson@...nel.org, konradybcio@...nel.org, vkoul@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-spi@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        dmaengine@...r.kernel.org
Cc: quic_varada@...cinc.com
Subject: Re: [PATCH 3/9] dma: qcom: bam_dma: Fix command element mask field
 for BAM v1.6.0+

On 9/19/25 7:56 AM, Md Sadre Alam wrote:
> 
> 
> On 9/18/2025 3:57 PM, Konrad Dybcio wrote:
>> On 9/18/25 11:40 AM, Md Sadre Alam wrote:
>>> BAM version 1.6.0 and later changed the behavior of the mask field in
>>> command elements for read operations. In newer BAM versions, the mask
>>> field for read commands contains the upper 4 bits of the destination
>>> address to support 36-bit addressing, while for write commands it
>>> continues to function as a traditional write mask.
>>
>> So the hardware can read from higher addresses but not write to them?
> No,
> Write Operations: Can target any 32-bit address in the peripheral address space (up to 4GB)
> 
> Read Operations: Can read from any 32-bit peripheral address and
> place the data into 36-bit memory addresses (up to 64GB) starting
> from BAM v1.6.0

OK I misread your commit message

[...]

> For Read Commands:
> - BAM < v1.6.0: 3rd Dword completely ignored by hardware
> - BAM >= v1.6.0: 3rd Dword[3:0] contains upper 4 bits of destination
> address

This is important to point out. With that, the change looks sane indeed

Konrad

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