Message-ID: <mafs05xcpo9sz.fsf@kernel.org>
Date: Wed, 08 Oct 2025 14:30:20 +0200
From: Pratyush Yadav <pratyush@...nel.org>
To: Sean Anderson <sean.anderson@...ux.dev>
Cc: Pratyush Yadav <pratyush@...nel.org>,  Tudor Ambarus
 <tudor.ambarus@...aro.org>,  Michael Walle <mwalle@...nel.org>,
  linux-mtd@...ts.infradead.org,  Richard Weinberger <richard@....at>,
  linux-kernel@...r.kernel.org,  Miquel Raynal <miquel.raynal@...tlin.com>,
  Vignesh Raghavendra <vigneshr@...com>
Subject: Re: [PATCH] mtd: spi-nor: Enable locking for n25q00a

On Tue, Oct 07 2025, Sean Anderson wrote:

> On 10/7/25 09:15, Pratyush Yadav wrote:
>> On Mon, Oct 06 2025, Sean Anderson wrote:
>> 
>>> The datasheet for n25q00a shows that the status register has the same
>>> layout as for n25q00, so use the same flags to enable locking support.
>>> These flags should have been added back in commit 150ccc181588 ("mtd:
>>> spi-nor: Enable locking for n25q128a11"), but they were removed by the
>>> maintainer...
>> 
>> This makes it sound like the maintainer did something wrong, which is
>> not true. Tudor had a good reason for removing them.
>
> I disagree. The maintainer used his position of authority to make the
> submitter second-guess their correct patch.

Sean, you are being very combative over such a small issue. You must
test your changes. This is one of the most basic principles in software
engineering. It was perfectly reasonable from Tudor to push back on
untested changes.

There is no abuse of "position of authority" here. When things break, we
get to do the work of putting the pieces back together. So of course, we
are reluctant to take things that increase this burden for us. Having
contributors test their changes is the simplest of things we ask for to
keep the quality bar.

Beyond that, I'd say that a little politeness goes a long way in life.
Especially towards the people maintaining the software for free that you
(or your employer) use. We are both wasting our energy on this debate.
Please stop. Take a step back and think from the other side's
perspective. And try to work _with_ people, not against them.

>
> These flashes have capacity of greater than the 8 MiB that can be
> protected using 3 BP bits. Micron (and ST before them?) addressed this
> by adding a fourth BP bit. This is consistent across every flash in this
> series, and is clearly documented in every datasheet. Defaulting to 3
> bits is buggy behavior: we should assume flashes behave per their
> datasheets until proven otherwise, especially for less-popular features

If I had a euro every time I found a bug in a datasheet, well, I would
have enough money to at least buy a nice dinner. My point is, datasheets
are not perfect. Only running on real hardware gets you the true
picture.

> that the original submitter may not have tested.
>
> The original patch was entirely correct, and the maintainer's
> justification for removing the second hunk is flawed.
>
>> Jungseung did not
>> have the flash at hand and Tudor didn't want to apply patches that
>> weren't tested. Both were in agreement for removing the n25q00a changes.
>> 
>> If you are going to mention that commit, then mention the full context,
>> and then also mention what has changed since that makes it possible to
>> add those changes back in. Having tested them on the real hardware for
>> example.
>> 
>>>
>>> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
>>> ---
>>> Tested with a mt25qu01gbbb, which shares the same flash ID.
>> 
>> Ughh, is this another case of flash ID reuse? Do mt25qu and n25q00a
>> flashes behave exactly the same and only have two names? If not, then
>> how do you know if n25q00a will also work with these changes?
>
> I examined the datasheet for the n25q00a and determined that it has the
> same status register layout.

Can you share the links to the datasheets?

Also, test logs would be nice to have.

>
> In fact, every n25q and mt25q flash has the same status register layout,
> which (as noted above) is necessary to support capacities greater than 8
> MiB (and all flashes in this series have such capacity).

Do they behave the same? If not, do you know how they differ? If they
behave differently, we might need to have some code that detects which
one is running. Not necessarily as part of this patch though.

>
> --Sea
>
>>>
>>>  drivers/mtd/spi-nor/micron-st.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
>>> index 187239ccd549..17c7d6322508 100644
>>> --- a/drivers/mtd/spi-nor/micron-st.c
>>> +++ b/drivers/mtd/spi-nor/micron-st.c
>>> @@ -486,6 +486,8 @@ static const struct flash_info st_nor_parts[] = {
>>>  		.id = SNOR_ID(0x20, 0xbb, 0x21),
>>>  		.name = "n25q00a",
>>>  		.size = SZ_128M,
>>> +		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
>>> +			 SPI_NOR_BP3_SR_BIT6,
>>>  		.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
>>>  		.mfr_flags = USE_FSR,
>>>  		.fixups = &n25q00_fixups,
>> 

-- 
Regards,
Pratyush Yadav

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