linux-kernel - Re: [PATCH v5] ASoC: wm8978: add missing BCLK divider setup

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Message-ID: <CAN7C2SCXibPFB50TfNLxmwf--wPVUewNQ1LM4T4fEy2Kioo=sg@mail.gmail.com>
Date: Thu, 9 Oct 2025 02:22:53 +0800
From: Sune Brian <briansune@...il.com>
To: Charles Keepax <ckeepax@...nsource.cirrus.com>
Cc: Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, 
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>, linux-sound@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5] ASoC: wm8978: add missing BCLK divider setup

Charles Keepax <ckeepax@...nsource.cirrus.com> 於 2025年10月9日 週四 上午1:16寫道：

> [1] https://www.nxp.com/docs/en/user-manual/UM11732.pdf

I am curious. With this codec WM8978.
Can you set a LRCLK rate that is not relied on MCLK+BCLK ratio from
first place when codec is in master mode.
Can you request a sample rate that requires the concept of extra bit
clock arbitrary higher in one extra order?
Very curious on such idea.

If possible maybe some examples can help.