linux-kernel - Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller

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Message-ID: <4kvo2qg2til22hlssv7lt2ugo63emr5c4hfjur5m3vnxvpdekx@jcbhaxb2d2j2>
Date: Thu, 9 Oct 2025 11:47:09 -0700
From: Manivannan Sadhasivam <mani@...nel.org>
To: Arnd Bergmann <arnd@...db.de>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Vincent Guittot <vincent.guittot@...aro.org>, Chester Lin <chester62515@...il.com>, 
	Matthias Brugger <mbrugger@...e.com>, Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>, 
	NXP S32 Linux Team <s32@....com>, bhelgaas@...gle.com, jingoohan1@...il.com, 
	Krzysztof Wilczyński <kwilczynski@...nel.org>, Rob Herring <robh@...nel.org>, krzk+dt@...nel.org, 
	Conor Dooley <conor+dt@...nel.org>, Ionut.Vicovan@....com, Larisa Grigore <larisa.grigore@....com>, 
	Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>, ciprianmarian.costea@....com, 
	Bogdan Hamciuc <bogdan.hamciuc@....com>, Frank Li <Frank.li@....com>, 
	linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, imx@...ts.linux.dev, Niklas Cassel <cassel@...nel.org>
Subject: Re: [PATCH 1/3 v2] dt-bindings: PCI: s32g: Add NXP PCIe controller

On Wed, Oct 08, 2025 at 07:56:44PM +0200, Arnd Bergmann wrote:
> On Wed, Oct 8, 2025, at 17:19, Manivannan Sadhasivam wrote:
> > On Wed, Oct 08, 2025 at 10:35:34AM +0200, Arnd Bergmann wrote:
> >> On Wed, Oct 8, 2025, at 10:26, Arnd Bergmann wrote:
> >> > the physical addresses for RAM at 0x80000000 and on-chip devices
> >> > at 0x40000000. This probably works fine as long as the total
> >> > PCI memory space assignment stays below 0x40000000 but would
> >> > fail once addresses actually start clashing.
> >> 
> >> I got confused here myself, but what I should have said is that
> >> having the DMA address for the RAM overlap the BAR space
> >> as seen from PCI is problematic as the PCI host bridge
> >> cannot tell PCI P2P transfers from DMA to RAM, so one
> >> of them will be broken here.
> >> 
> >
> > No. The IP just sets up the outbound mapping here for the entire 'ranges'. When
> > P2P happens, it will use the inbound mapping translation.
> 
> That is not my impression from reading the code: At least for
> the case where both devices are on the same bridge and they
> use map_type=PCI_P2PDMA_MAP_BUS_ADDR, I would expect the DMA
> to use the plain PCI bus address, not going through the
> dma-ranges+ranges translation that would apply when they are
> on different host bridges.
> 

Right, but I don't get the overlap issue still. If the P2P client triggers a
write to a P2P PCI address (let's assume 0x8000_0000), and if that address
belongs to a an endpoint in a different domain, the host bridge should still
forward it to the endpoint without triggering write to the RAM.

Atleast, I don't see any concern from the outbound memory translation point of
view.

Please let me know if there is any gap in my understanding.

- Mani

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