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Message-ID: <b8105d25-112c-4406-9f3a-8fbbd0754b26@amlogic.com> Date: Thu, 9 Oct 2025 11:09:25 +0800 From: Chuan Liu <chuan.liu@...ogic.com> To: Jerome Brunet <jbrunet@...libre.com>, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org> Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Neil Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-amlogic@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, Xianwei Zhao <xianwei.zhao@...ogic.com> Subject: Re: [PATCH 00/19] clk: amlogic: Add PLLs and peripheral clocks for A4 and A5 SoCs Hi Jerome, Thanks for your review, because the national day holidays did not timely feedback. On 10/1/2025 3:45 PM, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Tue 30 Sep 2025 at 17:37, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@...nel.org> wrote: > >> This patch series includes changes related to the PLL and peripheral >> clocks for both the A4 and A5 SoCs. >> >> The patches for A5 were previously submitted up to V3 by Xianwei. >> https://lore.kernel.org/all/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com/ >> After friendly coordination, I’ve taken over and continued the >> submission as part of this series. The dt-bindings patch retains Rob's >> original "Reviewed-by" tag, and I hope this hasn’t caused any >> additional confusion. > ... and yet you restart the versioning of the series making it harder > for people to follow that Sorry for the inconvenience caused. The main changes compared to the previous version by Xianwei are in the driver part. The dt-bindings part only has minor modifications in [PATCH 14/19]. The driver part has relatively larger changes because it needs to be based on the code base you previously submitted. >> Both A4 and A5 belong to the Audio series. Judging by their names, one >> might assume that A5 is an upgrade to A4, but in fact, A5 was released >> a year earlier than A4. >> >> Since there are differences in the PLLs and peripheral clocks between >> the A4 and A5 SoCs (especially the PLL), and taking into account factors >> such as memory footprint and maintainability, this series does not >> attempt to merge the two into a shared driver as was done for >> G12A/G12B/SM1. > ... and we end up with 19 patches series while it could be splitted into > manageable series, for each controller of each SoC I'm not sure if I understood you correctly. Do you mean that I should split this series of 19 patches into multiple patch series and send them separately? For example: serie 1: A4 SCMI clock controller (dt-bindings) serie 2: A4 PLL clock controller (dt-bindings, driver, dts) serie 3: A4 peripherals clock controller (dt-bindings, driver, dts) ... A5 similarly? >> This patch series includes all related dt-bindings, driver, and dts >> changes for the PLLs and peripheral clocks. Following our past convention >> for clock-related submissions, the dts changes are placed at the end >> and submitted separately. If this ordering makes it harder for >> maintainers to review or pick patches, please feel free to point it out. >> >> Co-developed-by: Xianwei Zhao <xianwei.zhao@...ogic.com> >> Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com> >> Signed-off-by: Chuan Liu <chuan.liu@...ogic.com> >> --- >> Chuan Liu (19): >> dt-bindings: clock: Add Amlogic A4 SCMI clock controller >> dt-bindings: clock: Add Amlogic A4 PLL clock controller >> dt-bindings: clock: Add Amlogic A4 peripherals clock controller >> clk: amlogic: Optimize PLL enable timing >> clk: amlogic: Correct l_detect bit control >> clk: amlogic: Fix out-of-range PLL frequency setting >> clk: amlogic: Add A4 PLL clock controller driver >> clk: amlogic: Add A4 clock peripherals controller driver >> arm64: dts: amlogic: A4: Add scmi-clk node >> arm64: dts: amlogic: A4: Add PLL controller node >> arm64: dts: amlogic: A4: Add peripherals clock controller node >> dt-bindings: clock: Add Amlogic A5 SCMI clock controller support >> dt-bindings: clock: Add Amlogic A5 PLL clock controller >> dt-bindings: clock: Add Amlogic A5 peripherals clock controller >> clk: amlogic: Add A5 PLL clock controller driver >> clk: amlogic: Add A5 clock peripherals controller driver >> arm64: dts: amlogic: A5: Add scmi-clk node >> arm64: dts: amlogic: A5: Add PLL controller node >> arm64: dts: amlogic: A5: Add peripheral clock controller node >> >> .../clock/amlogic,a4-peripherals-clkc.yaml | 122 +++ >> .../bindings/clock/amlogic,a4-pll-clkc.yaml | 61 ++ >> .../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++ >> .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++ >> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 80 ++ >> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 87 ++ >> drivers/clk/meson/Kconfig | 53 ++ >> drivers/clk/meson/Makefile | 4 + >> drivers/clk/meson/a1-pll.c | 1 + >> drivers/clk/meson/a4-peripherals.c | 764 ++++++++++++++++++ >> drivers/clk/meson/a4-pll.c | 242 ++++++ >> drivers/clk/meson/a5-peripherals.c | 883 +++++++++++++++++++++ >> drivers/clk/meson/a5-pll.c | 476 +++++++++++ >> drivers/clk/meson/clk-pll.c | 76 +- >> drivers/clk/meson/clk-pll.h | 2 + >> .../clock/amlogic,a4-peripherals-clkc.h | 129 +++ >> include/dt-bindings/clock/amlogic,a4-pll-clkc.h | 15 + >> include/dt-bindings/clock/amlogic,a4-scmi-clkc.h | 42 + >> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++ >> include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 + >> include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 + >> 21 files changed, 3406 insertions(+), 28 deletions(-) >> --- >> base-commit: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf >> change-id: 20250928-a4_a5_add_clock_driver-2b7c9d695633 >> >> Best regards, > -- > Jerome
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