[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <g6mv3ebxukceroa76w7s4s6tosqy34mj4xvzfwzozimdbkh5hx@b36drutn3lfl>
Date: Fri, 10 Oct 2025 00:59:59 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Alexey Minnekhanov <alexeymin@...tmarketos.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...il.com>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sdm630: fix gpu_speed_bin size
On Thu, Oct 09, 2025 at 09:41:13PM +0300, Alexey Minnekhanov wrote:
> On 06.10.2025 01:16, Dmitry Baryshkov wrote:
> > Historically sdm630.dtsi has used 1 byte length for the gpu_speed_bin
> > cell, although it spans two bytes (offset 5, size 7 bits). It was being
> > accepted by the kernel because before the commit 7a06ef751077 ("nvmem:
> > core: fix bit offsets of more than one byte") the kernel didn't have
> > length check. After this commit nvmem core rejects QFPROM on sdm630 /
> > sdm660, making GPU and USB unusable on those platforms.
> >
> > Set the size of the gpu_speed_bin cell to 2 bytes, fixing the parsing
> > error.
> >
> > Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file")
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > index 8b1a45a4e56ed1ae02e5bb6e78ca6255d87add1c..21f7dcf60679026e45202c6ce137ca0463c00d0e 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > @@ -598,7 +598,7 @@ qusb2_hstx_trim: hstx-trim@240 {
> > };
> > gpu_speed_bin: gpu-speed-bin@...0 {
> > - reg = <0x41a2 0x1>;
> > + reg = <0x41a2 0x2>;
> > bits = <5 7>;
> > };
> > };
>
> Hi Dmitry,
>
> I think bits should be <5 8> as well.
>
> I had similar fix in [1] for quite some time with a bit longer
Indeed, it looks so. Please post your patch!
> explanation why. In short, we need 8 bits to be able to read the
> value in speedbin efuse fully. Currently on my device
> (sdm660-xiaomi-laevnder) the resulting value in Adreno driver is
> 0x7. There is no such speedbin in [2]. It should read 0x87 (135)
> which corresponds to downstream's qcom,gpu-pwrlevels-3 with 647
> MHz max, which is further confirmed by testing on the device running
> Android by doing:
>
> cat /sys/kernel/gpu/gpu_max_clock
>
> Which will show 647, confirming that 0x87 should be the bin.
>
> Also when you look at the list of speedbins downstream [2] [3] for each
> SoC you'll see:
>
> * SDM636/660: 157 (0x9d), 146 (0x92), 135 (0x87), 122 (0x7a),
> 90 (0x5a), 78 (0x4e)
> * SDM630: 162 (0xa2), 146 (0x92), 135 (0x87)
>
> it becomes clear that 7 bits are not enough to hold values above 127.
> Therefore we need 8 bits.
>
> [1] https://github.com/sdm660-mainline/linux/commit/f9f92384794ca792a622ed19d5b5d2dac73a1a78
> [2] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi
> [3] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/arch/arm/boot/dts/qcom/sdm630-gpu.dtsi
>
> --
> Regards,
> Alexey Minnekhanov
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists