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Message-Id: <20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-4-2a34d8d03c72@oss.qualcomm.com>
Date: Thu, 09 Oct 2025 11:48:54 +0530
From: Abhinaba Rakshit <abhinaba.rakshit@....qualcomm.com>
To: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>
Cc: linux-arm-msm@...r.kernel.org, linux-mmc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-crypto@...r.kernel.org,
Abhinaba Rakshit <abhinaba.rakshit@....qualcomm.com>
Subject: [PATCH 4/5] arm64: dts: qcom: qcs615: add ufs and emmc inline
crypto engine nodes
Add separate ICE nodes for eMMC and UFS for QCS615 platform.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm6150.dtsi | 51 +++++++++++++++++++++---------------
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 3d2a1cb02b628a5db7ca14bea784429be5a020f9..bc1167b86e3896b9a54290e6a55ee2fa75a48c27 100644
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -549,11 +549,9 @@ rng@...000 {
sdhc_1: mmc@...000 {
compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x007c4000 0x0 0x1000>,
- <0x0 0x007c5000 0x0 0x1000>,
- <0x0 0x007c8000 0x0 0x8000>;
+ <0x0 0x007c5000 0x0 0x1000>;
reg-names = "hc",
- "cqhci",
- "ice";
+ "cqhci";
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
@@ -562,12 +560,10 @@ sdhc_1: mmc@...000 {
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ <&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"core",
- "xo",
- "ice";
+ "xo";
resets = <&gcc GCC_SDCC1_BCR>;
@@ -587,6 +583,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
dma-coherent;
status = "disabled";
+ qcom,ice = <&ice_mmc>;
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -613,6 +610,15 @@ opp-384000000 {
};
};
+ ice_mmc: crypto@...000 {
+ compatible = "qcom,qcs615-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x7c8000 0x0 0x8000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ freq-table-hz = <75000000 300000000>;
+ status = "disabled";
+ };
+
gpi_dma0: dma-controller@...000 {
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0x800000 0x0 0x60000>;
@@ -1249,10 +1255,8 @@ pcie_phy: phy@...e000 {
ufs_mem_hc: ufshc@...4000 {
compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
- reg = <0x0 0x01d84000 0x0 0x3000>,
- <0x0 0x01d90000 0x0 0x8000>;
- reg-names = "std",
- "ice";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+ reg-names = "std";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@@ -1260,7 +1264,6 @@ ufs_mem_hc: ufshc@...4000 {
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
@@ -1270,8 +1273,7 @@ ufs_mem_hc: ufshc@...4000 {
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "ice_core_clk";
+ "rx_lane0_sync_clk";
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
@@ -1297,6 +1299,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
#reset-cells = <1>;
status = "disabled";
+ qcom,ice = <&ice>;
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1308,8 +1311,7 @@ opp-50000000 {
/bits/ 64 <37500000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
- /bits/ 64 <0>,
- /bits/ 64 <75000000>;
+ /bits/ 64 <0>;
required-opps = <&rpmhpd_opp_low_svs>;
};
@@ -1320,8 +1322,7 @@ opp-100000000 {
/bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
- /bits/ 64 <0>,
- /bits/ 64 <150000000>;
+ /bits/ 64 <0>;
required-opps = <&rpmhpd_opp_svs>;
};
@@ -1332,8 +1333,7 @@ opp-200000000 {
/bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
- /bits/ 64 <0>,
- /bits/ 64 <300000000>;
+ /bits/ 64 <0>;
required-opps = <&rpmhpd_opp_nom>;
};
};
@@ -1360,6 +1360,15 @@ ufs_mem_phy: phy@...7000 {
status = "disabled";
};
+ ice: crypto@...0000 {
+ compatible = "qcom,qcs615-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x01d90000 0x0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ freq-table-hz = <75000000 300000000>;
+ status = "disabled";
+ };
+
cryptobam: dma-controller@...4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x24000>;
--
2.34.1
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