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Message-Id: <20251009071127.26026-5-quic_riteshk@quicinc.com>
Date: Thu, 9 Oct 2025 12:41:26 +0530
From: Ritesh Kumar <quic_riteshk@...cinc.com>
To: robin.clark@....qualcomm.com, lumag@...nel.org, abhinav.kumar@...ux.dev,
jessica.zhang@....qualcomm.com, sean@...rly.run,
marijn.suijten@...ainline.org, maarten.lankhorst@...ux.intel.com,
mripard@...nel.org, tzimmermann@...e.de, airlied@...il.com,
simona@...ll.ch, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, quic_mahap@...cinc.com, andersson@...nel.org,
konradybcio@...nel.org, mani@...nel.org,
James.Bottomley@...senPartnership.com, martin.petersen@...cle.com,
vkoul@...nel.org, kishon@...nel.org,
cros-qcom-dts-watchers@...omium.org
Cc: Ritesh Kumar <quic_riteshk@...cinc.com>, linux-phy@...ts.infradead.org,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-scsi@...r.kernel.org,
quic_vproddut@...cinc.com
Subject: [PATCH 4/5] arm64: dts: qcom: Add edp reference clock for edp phy
Add edp reference clock for edp phy on lemans, sc7280
and x1e80100 chipsets.
Signed-off-by: Ritesh Kumar <quic_riteshk@...cinc.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++----
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++--
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++----
3 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index cf685cb186ed..e8deb50f248b 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5034,9 +5034,11 @@
<0x0 0x0aec2000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "edp_ref";
#clock-cells = <1>;
#phy-cells = <0>;
@@ -5053,9 +5055,11 @@
<0x0 0x0aec5000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "edp_ref";
#clock-cells = <1>;
#phy-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4b04dea57ec8..1af79bddcf38 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5222,10 +5222,12 @@
<0 0x0aec2600 0 0xa0>,
<0 0x0aec2000 0 0x1c0>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
+ clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_EDP_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "edp_ref";
#clock-cells = <1>;
#phy-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 51576d9c935d..c42c292267cc 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5817,9 +5817,11 @@
<0 0x0aec2000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "edp_ref";
power-domains = <&rpmhpd RPMHPD_MX>;
@@ -5837,9 +5839,11 @@
<0 0x0aec5000 0 0x1c8>;
clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
- <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&tcsr TCSR_EDP_CLKREF_EN>;
clock-names = "aux",
- "cfg_ahb";
+ "cfg_ahb",
+ "edp_ref";
power-domains = <&rpmhpd RPMHPD_MX>;
--
2.17.1
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