Message-ID: <9ee299c1-edf4-4738-8b5e-6a684f683fbd@kernel.org>
Date: Thu, 9 Oct 2025 16:26:08 +0900
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Roy Luo <royluo@...gle.com>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I
 <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Peter Griffin <peter.griffin@...aro.org>,
 André Draszik <andre.draszik@...aro.org>,
 Tudor Ambarus <tudor.ambarus@...aro.org>,
 Joy Chakraborty <joychakr@...gle.com>, Naveen Kumar <mnkumar@...gle.com>,
 Badhri Jagan Sridharan <badhri@...gle.com>, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-usb@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v2 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3

On 09/10/2025 14:12, Roy Luo wrote:
> On Wed, Oct 8, 2025 at 4:56 PM Krzysztof Kozlowski <krzk@...nel.org> wrote:
>>
>> On 08/10/2025 14:59, Roy Luo wrote:
>>> Document the device tree bindings for the DWC3 USB controller found in
>>> Google Tensor SoCs, starting with the G5 generation.
>>>
>>> The Tensor G5 silicon represents a complete architectural departure from
>>
>>
>> G5 does not have a model number like G1-G4?
> 
> There's no model number for G5, I'm sticking to the existing "gs" prefix
> as they're still in the same SoC family.  Please let me know if you have any
> concerns.
> 
>>
>>> previous generations (like gs101), including entirely new clock/reset
>>> schemes, top-level wrapper and register interface. Consequently,
>>> existing Samsung/Exynos DWC3 USB bindings and drivers are incompatible,
>>
>> Do not reference drivers. Explain the hardware.
> 
> Ack, all mentions of "driver" will be removed in the next patch.
> 
>>
>>> necessitating this new device tree binding.
>>>
>>> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
>>> Dual-Role Device single port with hibernation support.
>>>
>>> Signed-off-by: Roy Luo <royluo@...gle.com>
>>> ---
>>>  .../bindings/usb/google,gs-dwc3.yaml          | 145 ++++++++++++++++++
>>>  1 file changed, 145 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
>>> new file mode 100644
>>> index 000000000000..9eb0bf726e8d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
>>> @@ -0,0 +1,145 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +# Copyright (c) 2025, Google LLC
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/usb/google,gs-dwc3.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
>>> +
>>> +maintainers:
>>> +  - Roy Luo <royluo@...gle.com>
>>> +
>>> +description: |
>>
>>
>> Do not need '|' unless you need to preserve formatting.
> 
> Ack, will fix this in the next patch.
> 
>>
>>> +  Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
>>> +  starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
>>> +  features Dual-Role Device single port with hibernation add-on.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - enum:
>>> +          - google,gs5-dwc3
>>> +
>>> +  reg:
>>> +    minItems: 3
>>
>> Drop
>>
>>> +    maxItems: 3
>>> +
>>> +  reg-names:
>>> +    description: |
>>> +      The following memory regions must present:
>>> +        - dwc3_core: Core DWC3 IP registers.
>>> +        - host_cfg_csr: Hibernation control registers.
>>> +        - usbint_csr: Hibernation interrupt registers.
>>
>> Drop description or move it to items in reg. See other bindings.
> 
> Ack, will use an item list in reg instead.
> 
>>
>>> +    items:
>>> +      - const: dwc3_core
>>> +      - const: host_cfg_csr
>>> +      - const: usbint_csr
>>> +
>>> +  interrupts:
>>> +    minItems: 3
>>
>> Drop
> 
> Ack, will use an item list instead.
> 
>>
>>> +    maxItems: 3
>>> +
>>> +  interrupt-names:
>>> +    description: |
>>> +      The following interrupts must present:
>>> +        - dwc_usb3: Core DWC3 interrupt.
>>> +        - hs_pme_irq: High speed remote wakeup interrupt for hibernation.
>>> +        - ss_pme_irq: Super speed remote wakeup interrupt for hibernation.
>>
>> From where did you get this style? Don't write bindings with chat gpt or
>> whatever other tool. it is a waste of our time.
> 
> I referenced the style from a recent dt binding change [1] that adds
> "Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml".
> I thought it would be a good reference because it's relatively new
> and is also a binding for SNPS dwc3 glue logic. Perhaps that style
> doesn't apply here because qcom,snps-dwc3.yaml supports
> multiple compatible and here we have only one?
> 
> Just to clarify, I'm a Gemini user and this patch is 100% organic,
> hand-crafted by a living human brain :)
> 
> [1] https://lore.kernel.org/all/20250414-dwc3-refactor-v7-2-f015b358722d@oss.qualcomm.com/

Your code is not at all like above, you do not have any variants here,
so you cannot use that syntax - is not correct here.

Best regards,
Krzysztof

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