linux-kernel - Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox

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Message-ID: <ca4853a1-67e7-4152-aea1-f92c9c25d7eb@oss.qualcomm.com>
Date: Thu, 9 Oct 2025 16:13:35 +0530
From: Sibi Sankar <sibi.sankar@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Pankaj Patil <pankaj.patil@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox


On 9/25/2025 3:59 PM, Konrad Dybcio wrote:
> On 9/25/25 8:32 AM, Pankaj Patil wrote:
>> From: Sibi Sankar <sibi.sankar@....qualcomm.com>
>>
>> Enable pdp0 mailbox node on Glymur SoCs.
>>
>> Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
>> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -4065,6 +4065,14 @@ watchdog@...00000 {
>>   			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
>>   		};
>>   
>> +		pdp0_mbox: mailbox@...10000 {
>> +			compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
>> +			reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> 1 a line, please

Hey Konrad,

Thanks for taking time to review the series :)

Will fix it in the next re-spin.

>> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> I see this has 3 channels, with 3 separate IRQs (but one pair of address
> spaces) - should we extend this description?

It has a single IRQ and each bit corresponds to a channel.  The mbox 
theoretically

hold as many channel as the number of bits. The third channel here is 
used for

logging and is disabled on devices out in the wild.

>
>> +			#mbox-cells = <1>;
>> +			qcom,rx-chans = <0x7>;
> This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7)
> however this property doesn't exist upstream..

Ack, this seems to have picked up erroneously and isn't needed upstream and

can be dropped safely. This was needed downstream because they share the

same rx register space across multiple instances. This wouldn't be possible

upstream and we would be exposing all mailboxes that uses the rx space in

the same instance and extend mbox cells to 2 to support this in case when

it is needed in the future.

> Konrad