linux-kernel - [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key

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Message-ID: <20251009134318.23040-2-zihong.plct@isrc.iscas.ac.cn>
Date: Thu,  9 Oct 2025 21:41:51 +0800
From: Yao Zihong <zihong.plct@...c.iscas.ac.cn>
To: linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: ajones@...tanamicro.com,
	alexghiti@...osinc.com,
	shuah@...nel.org,
	samuel.holland@...ive.com,
	evan@...osinc.com,
	cleger@...osinc.com,
	zihong.plct@...c.iscas.ac.cn,
	zihongyao@...look.com,
	zhangyin2018@...as.ac.cn,
	Paul Walmsley <pjw@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alex@...ti.fr>,
	Charlie Jenkins <charlie@...osinc.com>,
	Cyan Yang <cyan.yang@...ive.com>,
	Yunhui Cui <cuiyunhui@...edance.com>,
	Aleksa Paunovic <aleksa.paunovic@...cgroup.com>,
	Jesse Taube <jesse@...osinc.com>,
	Inochi Amaoto <inochiama@...il.com>
Subject: [PATCH v2 1/4] uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key

Introduce RISCV_HWPROBE_EXT_ZICBOP to report presence of the Zicbop
extension through hwprobe, and add RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE
to expose the block size (in bytes) when Zicbop is supported.

Signed-off-by: Yao Zihong <zihong.plct@...c.iscas.ac.cn>
---
 arch/riscv/include/asm/hwprobe.h      | 2 +-
 arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 948d2b34e94e..2f278c395af9 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 14
+#define RISCV_HWPROBE_MAX_KEY 15
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 5d30a4fae37a..9cc508be54c5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -82,6 +82,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZAAMO		(1ULL << 56)
 #define		RISCV_HWPROBE_EXT_ZALRSC	(1ULL << 57)
 #define		RISCV_HWPROBE_EXT_ZABHA		(1ULL << 58)
+#define		RISCV_HWPROBE_EXT_ZICBOP	(1ULL << 59)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
@@ -107,6 +108,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
+#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE	15
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
-- 
2.47.2